# RTL Mini Projects - SystemVerilog
This repository contains a collection of RTL mini projects developed as part of my continued learning in digital design and VLSI front-end using SystemVerilog. Each project focuses on strengthening understanding of FSM-based control, datapath design, reusable RTL modules, and timing-aware multi-cycle execution.
SystemVerilog is used in place of Verilog purely for learning purposes, to practice industry-style RTL coding approach while building synthesizable designs.
-> This repository represents Phase-1 Cycle-2: Control, Datapath & Timing-Aware RTL Design of my RTL learning journey, focused on building cycle-accurate, synthesizable RTL designs and understanding real hardware execution behavior.
The goal of this repository is to:
- Practice FSM-controlled and multi-cycle RTL design
- Understand control-datapath interaction
- Apply reg -> combinational -> reg timing discipline
- Build reusable and parameterized RTL blocks
- Verify designs using cycle-accurate testbenches
- Extend the RTL portfolio towards front-end VLSI roles
## Repository Structure
Control-Datapath-Timing-Aware-RTL-Design/
├── Week-5/ # Mini CPU Core (FSM + Datapath Basics)
├── Week-6/ # Reusable RTL Library (ALU, Registers, Counters)
├── Week-7/ # Timing-Aware Integrated Datapath
├── Week-8/ # FSM-Based Multi-Cycle Execution Engine
└── README.md
Each folder contains:
- RTL source files
- Testbench
- A dedicated README explaining the design
## Projects Overview
| Week | Projects | Key Concepts |
|---|---|---|
| 5 | Mini CPU Core | FSM control, datapath blocks, instruction flow |
| 6 | Reusable RTL Library | Parameterized RTL, modular design |
| 7 | Timing-Aware Datapath | reg -> comb -> reg timing, pipeline staging |
| 8 | Multi-Cycle Execution Engine | FSM-controlled multi-cycle execution |
## Tools & Skills
- SystemVerilog
- RTL Design
- FSM Design
- Datapath Design
- Timing-Aware RTL
- Multi-Cycle Execution
- Testbench Development
- HDL Simulation (ModelSim / EDA Playground)
- Linux & Git
## About Me
I'm an Electronics Engineering student specializing in VLSI Design and Technology, building strong foundations in RTL design and verification with a focus on control logic, datapath integration, and timing-aware hardware design for front-end VLSI roles.
# Author: MARK JUSTIN