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| 1 | +# TurboQuant on AMD Instinct MI300X & MI355X (ROCm/HIP) |
| 2 | + |
| 3 | +## Summary |
| 4 | + |
| 5 | +TurboQuant KV cache compression (turbo2/turbo3/turbo4) builds and runs correctly on AMD Instinct MI300X (gfx942) and MI355X (gfx950). MI300X requires zero code changes. MI355X requires adding CDNA4 arch defines to the HIP vendor header. |
| 6 | + |
| 7 | +## Test Environment |
| 8 | + |
| 9 | +| Component | MI300X | MI355X | |
| 10 | +|-----------|--------|--------| |
| 11 | +| GPU | MI300X (gfx942), 192 GB HBM3 | MI355X (gfx950), 288 GB HBM3e | |
| 12 | +| ROCm | 7.0.2 | 7.0.1 | |
| 13 | +| Wave Size | 64 | 64 | |
| 14 | +| Build | `-DAMDGPU_TARGETS="gfx942"` | `-DAMDGPU_TARGETS="gfx950"` | |
| 15 | +| Model | Qwen2.5-1.5B Q4_K_M (1.04 GiB) | same | |
| 16 | + |
| 17 | +## WHT Kernel Correctness |
| 18 | + |
| 19 | +Standalone roundtrip test (forward WHT → inverse WHT) confirms the Walsh-Hadamard Transform kernel works correctly on HIP with 64-wide wavefronts: |
| 20 | + |
| 21 | +``` |
| 22 | +=== TurboQuant WHT Roundtrip Test (HIP/gfx942) === |
| 23 | +Total elements: 512 (4 heads x 128 dim) |
| 24 | +Forward WHT zeros: 0 / 512 |
| 25 | +Roundtrip max error: 2.980232e-07 |
| 26 | +Roundtrip RMSE: 6.816018e-08 |
| 27 | +Result: PASS ✅ |
| 28 | +``` |
| 29 | + |
| 30 | +The kernel uses shared memory + `__syncthreads()` (no warp shuffles), so it works correctly with GCN's 64-thread wavefronts without modification. |
| 31 | + |
| 32 | +## Performance Results |
| 33 | + |
| 34 | +### MI300X (single GPU, Qwen2.5-1.5B Q4_K_M) |
| 35 | + |
| 36 | +| KV Cache | pp512 (tok/s) | tg128 (tok/s) | Prefill vs f16 | Decode vs f16 | |
| 37 | +|----------|--------------|--------------|----------------|---------------| |
| 38 | +| f16 | 24,453 ± 230 | 181.2 ± 2.0 | baseline | baseline | |
| 39 | +| turbo3 | ~25,200 | ~160 | **+3%** | 88% | |
| 40 | +| turbo4 | 25,427 ± 17 | 161.1 ± 0.2 | **+4%** | 89% | |
| 41 | + |
| 42 | +### MI355X (single GPU, Qwen2.5-1.5B Q4_K_M) |
| 43 | + |
| 44 | +| KV Cache | pp512 (tok/s) | tg128 (tok/s) | Prefill vs f16 | Decode vs f16 | |
| 45 | +|----------|--------------|--------------|----------------|---------------| |
| 46 | +| f16+FA | 40,013 ± 902 | 254.5 ± 1.0 | baseline | baseline | |
| 47 | +| turbo3 | 39,140 ± 475 | 162.3 ± 0.1 | 98% | 64% | |
| 48 | +| turbo4 | 39,232 ± 508 | 214.1 ± 0.7 | 98% | **84%** | |
| 49 | + |
| 50 | +### Key Observations |
| 51 | + |
| 52 | +1. **MI300X prefill is faster with TurboQuant** (+3-4%) — less KV cache data to write to HBM. |
| 53 | +2. **MI300X decode at 88-89% of f16** — consistent with Apple Silicon community results. |
| 54 | +3. **MI355X turbo4 decode at 84%** — turbo4 outperforms turbo3 in decode due to simpler 4-bit dequant. |
| 55 | +4. **MI355X turbo3 decode at 64%** — the 3-bit codebook + sign extraction is more expensive on gfx950. |
| 56 | +5. **MI355X non-FA MMQ path crashes** (xf32 MFMA issue) — turbo types force FA and work correctly. |
| 57 | + |
| 58 | +## Build Instructions |
| 59 | + |
| 60 | +```bash |
| 61 | +git clone https://github.com/TheTom/llama-cpp-turboquant.git |
| 62 | +cd llama-cpp-turboquant |
| 63 | +git checkout feature/turboquant-kv-cache |
| 64 | + |
| 65 | +# MI300X (gfx942) — works without code changes |
| 66 | +cmake -B build -DGGML_HIP=ON -DCMAKE_BUILD_TYPE=Release -DAMDGPU_TARGETS="gfx942" |
| 67 | +cmake --build build --config Release -j |
| 68 | + |
| 69 | +# MI355X (gfx950) — requires CDNA4 define patch (see commit) |
| 70 | +cmake -B build -DGGML_HIP=ON -DCMAKE_BUILD_TYPE=Release -DAMDGPU_TARGETS="gfx950" |
| 71 | +cmake --build build --config Release -j |
| 72 | + |
| 73 | +# Test |
| 74 | +HIP_VISIBLE_DEVICES=0 ./build/bin/llama-bench \ |
| 75 | + -m model.gguf -ctk turbo3 -ctv turbo3 -ngl 99 -r 3 -p 512 -n 128 |
| 76 | +``` |
| 77 | + |
| 78 | +## Code Changes for gfx950 (MI355X) |
| 79 | + |
| 80 | +Three files modified to add CDNA4 (gfx950) architecture support: |
| 81 | + |
| 82 | +1. **`ggml/src/ggml-cuda/vendors/hip.h`** — Add `CDNA4` define for `__gfx950__`, include in `CDNA` family |
| 83 | +2. **`ggml/src/ggml-cuda/common.cuh`** — Add `GGML_CUDA_CC_CDNA4` constant and `GGML_CUDA_CC_IS_CDNA4` macro |
| 84 | +3. **`ggml/src/ggml-cuda/mma.cuh`** — Route CDNA4 to compatible MFMA instructions (bf16_1k, i32x16x32_i8, f32x16x4f32 — NOT xf32 which doesn't exist on gfx950) |
| 85 | + |
| 86 | +## Known Limitations |
| 87 | + |
| 88 | +- **MI355X non-FA MMQ crashes**: The default (non-flash-attention) matrix multiply path crashes on gfx950 due to the xf32 MFMA instruction (`mfma_f32_16x16x8_xf32`) not being available. TurboQuant types force flash attention and work correctly. Standard f16/q8_0 KV cache types need `-fa 1` flag on MI355X. |
| 89 | +- **llama-cli text output**: Interactive mode produces empty tokens on ROCm (display issue), but `llama-bench` confirms computation is correct. |
| 90 | + |
| 91 | +## Tested By |
| 92 | + |
| 93 | +Andy Luo (@andyluo7) |
| 94 | +- AMD Instinct MI300X (gfx942), ROCm 7.0.2 — April 2026 |
| 95 | +- AMD Instinct MI355X (gfx950), ROCm 7.0.1 — April 2026 |
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