Signal legalization SSA rewrite needs

Author: AnastaZIuk

tools/clang/lib/SPIRV/SpirvEmitter.cpp

@@ -594,6 +594,7 @@ SpirvEmitter::SpirvEmitter(CompilerInstance &ci)
       curFunction(nullptr), curThis(nullptr), seenPushConstantAt(),
       isSpecConstantMode(false), needsLegalization(false),
       needsLegalizationLoopUnroll(false),
+      needsLegalizationSsaRewrite(false),
       beforeHlslLegalization(false), mainSourceFile(nullptr) {
 
   // Get ShaderModel from command line hlsl profile option.
@@ -955,6 +956,9 @@ void SpirvEmitter::HandleTranslationUnit(ASTContext &context) {
       declIdMapper.requiresFlatteningCompositeResources() ||
       !dsetbindingsToCombineImageSampler.empty() ||
       spirvOptions.signaturePacking;
+  needsLegalizationSsaRewrite =
+      needsLegalizationSsaRewrite ||
+      !dsetbindingsToCombineImageSampler.empty();
 
   // Run legalization passes
   if (spirvOptions.codeGenHighLevel) {
@@ -5827,6 +5831,7 @@ SpirvInstruction *SpirvEmitter::createImageSample(
   if (varOffset) {
     needsLegalization = true;
     needsLegalizationLoopUnroll = true;
+    needsLegalizationSsaRewrite = true;
   }
 
   // SampleDref* instructions in SPIR-V always return a scalar.
@@ -16669,7 +16674,8 @@ bool SpirvEmitter::spirvToolsLegalize(std::vector<uint32_t> *mod,
         spvtools::CreateInterfaceVariableScalarReplacementPass());
   }
   optimizer.RegisterLegalizationPasses(spirvOptions.preserveInterface,
-                                       needsLegalizationLoopUnroll);
+                                       needsLegalizationLoopUnroll,
+                                       needsLegalizationSsaRewrite);
   // Add flattening of resources if needed.
   if (spirvOptions.flattenResourceArrays) {
     optimizer.RegisterPass(

tools/clang/lib/SPIRV/SpirvEmitter.h

@@ -1579,6 +1579,7 @@ class SpirvEmitter : public ASTConsumer {
   /// Note: legalization specific code
   bool needsLegalization;
   bool needsLegalizationLoopUnroll;
+  bool needsLegalizationSsaRewrite;
 
   /// Whether the translated SPIR-V binary passes --before-hlsl-legalization
   /// option to spirv-val because of illegal function parameter scope.

tools/clang/test/CodeGenSPIRV/cast.flat-conversion.matrix.hlsl

@@ -16,11 +16,6 @@ RWStructuredBuffer<T> t_output;
 // COL: OpMemberDecorate %S 0 RowMajor
 // ROW: OpMemberDecorate %S 0 ColMajor
 
-// The DXIL generated for the two cases seem to produce the same results,
-// and this matches that behaviour.
-// CHECK: [[array_const:%[0-9]+]] = OpConstantComposite %_arr_float_uint_6 %float_0 %float_1 %float_2 %float_3 %float_4 %float_5
-// CHECK: [[t:%[0-9]+]] = OpConstantComposite %T [[array_const]]
-
 // The DXIL that is generates different order for the values depending on
 // whether the matrix is column or row major. However, for SPIR-V, the value
 // stored in both cases is the same because the decoration, which is checked
@@ -40,13 +35,16 @@ void main() {
       s.a[i][j] = i*3+j;
     }
   }
-// CHECK: [[ac:%[0-9]+]] = OpAccessChain %_ptr_Uniform_T %t_output %int_0 %uint_0
-// CHECK: OpStore [[ac]] [[t]]
+// CHECK: [[tptr:%[0-9]+]] = OpAccessChain %_ptr_Uniform_T %t_output %int_0 %uint_0
+// CHECK: [[tarr:%[0-9]+]] = OpCompositeConstruct %_arr_float_uint_6
+// CHECK: [[tval:%[0-9]+]] = OpCompositeConstruct %T [[tarr]]
+// CHECK: OpStore [[tptr]] [[tval]]
   T t = (T)(s);
   t_output[0] = t;
 
-// CHECK: [[ac:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %s_output %int_0 %uint_0
-// CHECK: OpStore [[ac]] [[s]]
+// CHECK: [[sptr:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %s_output %int_0 %uint_0
+// CHECK: [[sval:%[0-9]+]] = OpCompositeConstruct %S
+// CHECK: OpStore [[sptr]] [[sval]]
   s = (S)t;
   s_output[0] = s;
 }

tools/clang/test/CodeGenSPIRV/legal-examples/15-loop-var-unroll-ok.hlsl

@@ -1,14 +1,12 @@
 // RUN: %dxc -T cs_6_0 -E main -O3 -Vd %s -spirv | FileCheck %s
 
-// CHECK:      [[ptr:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %gSBuffer2
-// CHECK-NEXT: [[val:%[0-9]+]] = OpLoad %S [[ptr]]
-// CHECK-NEXT: [[ptr:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %gRWSBuffer
-// CHECK-NEXT:                OpStore [[ptr]] [[val]]
-
-// CHECK:      [[ptr:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %gSBuffer2
-// CHECK-NEXT: [[val:%[0-9]+]] = OpLoad %S [[ptr]]
-// CHECK-NEXT: [[ptr:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %gRWSBuffer
-// CHECK-NEXT:                OpStore [[ptr]] [[val]]
+// CHECK: OpLoopMerge {{%[0-9]+}} {{%[0-9]+}} Unroll
+// CHECK: [[which:%[0-9]+]] = OpSelect %_ptr_Uniform_type_StructuredBuffer_S {{%[0-9]+}} %gSBuffer1 %gSBuffer2
+// CHECK: [[idx:%[0-9]+]] = OpBitcast %uint {{%[0-9]+}}
+// CHECK: [[src:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S [[which]] %int_0 [[idx]]
+// CHECK: [[val:%[0-9]+]] = OpLoad %S [[src]]
+// CHECK: [[dst:%[0-9]+]] = OpAccessChain %_ptr_Uniform_S %gRWSBuffer %int_0 [[idx]]
+// CHECK: OpStore [[dst]] [[val]]
 
 struct S {
   float4 f;

tools/clang/test/CodeGenSPIRV/max_id.hlsl

@@ -8,7 +8,7 @@
 // CHECK-30: fatal error: failed to optimize SPIR-V: ID overflow. Try running compact-ids.
 
 // With a larger limit, the test case can compile successfully.
-// CHECK-400: Bound: 204
+// CHECK-400: Bound:
 
 
 RWStructuredBuffer<int> data;
@@ -20,4 +20,4 @@ void main(uint3 id : SV_DispatchThreadID)
   for( int i = 0; i < 64; i++ ) {
     data[i] = i;
   }
-}
+}