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mithromithro
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Merge branches 'travis-docs', 'isr-uart-i2c' and 'setupdat-comment'
4 parents 65cc7da + c0bcc69 + c9dd5fa + 3f1f0a4 commit 3590a1d

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‎.travis-push-docs.sh‎

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#!/bin/bash
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set -e
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if [ "$TRAVIS" = true -a "$TRAVIS_SECURE_ENV_VARS" = false ]; then
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echo "No environment variables found, skipping (probably a pull request)."
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exit 0
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fi
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if [ "$TRAVIS" = true -a "$TRAVIS_BRANCH" != "master" ]; then
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echo "No master branch, skipping."
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exit 0
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fi
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if [ -z "$TRAVIS_REPO_SLUG" ]; then
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echo "No TRAVIS_REPO_SLUG value found."
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echo "Please set this if running outside Travis."
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exit 0
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fi
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# FIXME: Replace this with a deploy key, so you don't end up with tokens which
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# potentially give people *a lot* of access to your GitHub repos.
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if [ -z "$GH_TOKEN" ]; then
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echo "No GH_TOKEN value found."
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echo
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echo "Generate a GitHub token at https://github.com/settings/tokens/new"
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echo "with *only* the public_repo option."
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echo "Then go to https://travis-ci.org/$TRAVIS_REPO_SLUG/settings and"
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echo "add an 'Environment Variables' with the following;"
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echo " * Name == GH_TOKEN"
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echo " * Value == your token value from above"
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echo " * Display value in build log == OFF"
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echo
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echo "It is important that you protect this token, as it has full push"
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echo "access to your repos!"
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exit 1
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fi
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if [ -z "$GIT_NAME" ]; then
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echo "No GIT_NAME value found."
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echo
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echo "Then go to https://travis-ci.org/$TRAVIS_REPO_SLUG/settings and"
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echo "add an 'Environment Variables' with the following;"
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echo " * Name == GIT_NAME"
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echo " * Value == Human readable name for the commit author."
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echo " Something like \"Tim Ansell's Robot\" is a good choice."
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echo " * Display value in build log == ON"
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exit 1
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fi
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if [ -z "$GIT_EMAIL" ]; then
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echo "No GIT_EMAIL value found."
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echo
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echo "Then go to https://travis-ci.org/$TRAVIS_REPO_SLUG/settings and"
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echo "add an 'Environment Variables' with the following;"
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echo " * Name == GIT_EMAIL"
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echo " * Value == Email address the commit author."
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echo " Set up an email address, or use your own."
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echo " * Display value in build log == ON"
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exit 1
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fi
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TMPDIR=$(mktemp --directory)
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if ! git describe > /dev/null 2>&1; then
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echo "- Fetching non shallow to get git version"
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git fetch --unshallow && git fetch --tags
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fi
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ORIG_GIT_REVISION=`git describe`
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ORIG_COMMITTER_NAME=$(git log -1 --pretty=%an)
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ORIG_COMMITTER_EMAIL=$(git log -1 --pretty=%ae)
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echo "- Setting up the output"
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cp -aRf docs/html/* $TMPDIR/
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cp docs/intro/intro.pdf $TMPDIR/
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find $TMPDIR | sort
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echo "- Switching to the gh-pages branch"
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git remote set-branches --add origin gh-pages
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git fetch origin gh-pages
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git checkout origin/gh-pages -b gh-pages
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echo "- Updating the README"
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sed -e"s-github.com/[^/]\+/[^/ ]\+-github.com/$TRAVIS_REPO_SLUG-" README.md > $TMPDIR/README.md
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cat $TMPDIR/README.md
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echo "- Adding the newly generated content"
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rm -rf *
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cp -aRf $TMPDIR/* .
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git add -v -A .
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echo "- Committing"
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export GIT_AUTHOR_EMAIL="$ORIG_COMMITTER_EMAIL"
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export GIT_AUTHOR_NAME="$ORIG_COMMITTER_NAME"
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export GIT_COMMITTER_EMAIL="$GIT_NAME"
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export GIT_COMMITTER_NAME="$GIT_EMAIL"
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unset GIT_NAME
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unset GIT_EMAIL
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git commit -a -m "Travis build #$TRAVIS_BUILD_NUMBER of $ORIG_GIT_REVISION"
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echo "- Pushing"
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git remote set-url origin https://$GH_TOKEN@github.com/$TRAVIS_REPO_SLUG.git > /dev/null 2>&1
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git push origin gh-pages > /dev/null 2>&1

‎.travis.yml‎

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@@ -10,6 +10,12 @@ install:
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- # Install sdcc
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- sudo apt-get install --force-yes -y sdcc
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- sdcc --version
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- # doxygen & rubber are needed for generating the documentation
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- sudo apt-get install -y doxygen rubber
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script:
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- make
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- make docs
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after_success:
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- ./.travis-push-docs.sh

‎include/fx2ints.h‎

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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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/*! \file
18-
* Define the standard fx2 interrupts. For int2 and int4 autovector
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* Define the standard FX2 interrupts. For INT2 and INT4 autovector
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* interrupts see \ref autovector.h
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*
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* To enable an interrupt, simply define an interrupt handler function
@@ -38,8 +38,7 @@
3838

3939

4040
/**
41-
* \brief interrupt numbers for standard fx2 interrupts
42-
41+
* \brief Interrupt numbers for standard FX2 interrupts.
4342
**/
4443
typedef enum {
4544
IE0_ISR=0, ///< External interrupt 0
@@ -50,29 +49,66 @@ typedef enum {
5049
TF2_ISR, ///< Timer 2 interrupt
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RESUME_ISR, ///< Resume interrupt
5251
TI_1_ISR, ///< Serial port 1 transmit or receive interrupt
53-
USBINT_ISR, ///< Usb Interrupt. An interrupt handler for this should only be used if not using auto vectored interrupts with int2
52+
USBINT_ISR, ///< USB Interrupt. An interrupt handler for this should only be used if not using auto vectored interrupts with INT2
5453
I2CINT_ISR, ///< I2C Bus interrupt
55-
IE4_ISR, ///< External interrupt 4. An interrupt handler for this should only be used if not using auto vectored interrupts with int4
54+
IE4_ISR, ///< External interrupt 4. An interrupt handler for this should only be used if not using auto vectored interrupts with INT4
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IE5_ISR, ///< External interrupt 5
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IE6_ISR, ///< External interrupt 6
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// Better names for the USART interrupts
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USART0_ISR = TI_0_ISR, ///< Better name for USART0 interrupt
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USART1_ISR = TI_1_ISR, ///< Better name for USART1 interrupt
5860
} FX2_ISR;
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/**
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* \brief Interrupt high priority.
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**/
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#define INTERRUPT_HIGH_PRIO 1
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/**
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* \brief Interrupt low priority.
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**/
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#define INTERRUPT_LOW_PRIO 0
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// TIMER0
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// =======================================================================
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6175
/**
6276
* \brief Enable the timer 0 interrupt.
6377
*
64-
* There is not CLEAR_TIMER0 because the timer interrupt flag
65-
* is automatically cleared when the isr is called.
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* CLEAR_TIMER0() is a NOP because the timer interrupt flag is automatically
79+
* cleared when the ISR is called.
6680
**/
6781
#define ENABLE_TIMER0() ET0=1
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/**
84+
* \brief Clear timer 0 interrupt
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*
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* CLEAR_TIMER0() is a NOP because the timer interrupt flag is automatically
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* cleared when the ISR is called.
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**/
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#define CLEAR_TIMER0()
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// TIMER1
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// =======================================================================
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6994
/**
7095
* \brief Enable timer 1 interrupt
71-
* There is no CLEAR_TIMER1 because the timer interrupt flag
72-
* is automatically cleared when the isr is called.
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*
97+
* CLEAR_TIMER1() is a NOP because the timer interrupt flag is automatically
98+
* cleared when the ISR is called.
7399
**/
74100
#define ENABLE_TIMER1() ET1=1
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/**
103+
* \brief Clear timer 1 interrupt
104+
*
105+
* CLEAR_TIMER1() is a NOP because the timer interrupt flag is automatically
106+
* cleared when the ISR is called.
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**/
108+
#define CLEAR_TIMER1()
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// TIMER2 and external EXF2 interrupt
111+
// =======================================================================
76112

77113
/**
78114
* \brief Enable timer 2 interrupt
@@ -82,12 +118,18 @@ typedef enum {
82118
**/
83119
#define ENABLE_TIMER2() ET2=1
84120
/**
85-
* \brief Clear timer 2 interrupt
121+
* \brief Clear timer 2 interrupt
86122
*
87-
* Clears both the TF2 AND EXF2 flag
123+
* Clears both the TF2 AND EXF2 flag
88124
**/
89125
#define CLEAR_TIMER2() TF2=0;EXF2=0;
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127+
// Resume interrupt
128+
// =======================================================================
129+
// After the FX2 has entered its idle state, it responds to an external signal
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// on its WAKEUP/WU2 pins or resumption of USB bus activity by restarting its
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// oscillator and resuming firmware execution.
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91133
/**
92134
* \brief Enable the Resume Interrupt. Requires EA=1 separately.
93135
**/
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99141
**/
100142
#define CLEAR_RESUME() RESI=0
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// Interrupt 4 - Autovectored FIFO / GPIF or External interrupt 4
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// =======================================================================
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103-
#define ENABLE_INT4()
147+
//#define ENABLE_INT4()
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149+
// External Interrupt 5
150+
// =======================================================================
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105152
/**
106153
* \brief
107-
* Enable external interupt for int5#
154+
* Enable external interrupt for INT5#
108155
**/
109156
#define ENABLE_INT5() EIEX5=1
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111158
/**
112159
* \brief
113-
* Clear int5# interrupt
160+
* Clear INT5# interrupt
161+
**/
162+
#define CLEAR_INT5() \
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EXIF &= ~bmIE5
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165+
// USART0
166+
// =======================================================================
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168+
/**
169+
* \brief Set the USART 0 interrupt priority.
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*
171+
* Does *not* enable the interrupt.
172+
*
173+
* \code
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* SET_USART0_ISR_PRIO(INTERRUPT_HIGH_PRIO); // Set USART0 to high priority
175+
* SET_USART0_ISR_PRIO(INTERRUPT_LOW_PRIO); // Set USART0 to low priority
176+
* \endcode
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**/
178+
#define SET_USART0_ISR_PRIORITY(p) \
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PS0 = p
180+
/**
181+
* \brief Enable the USART 0 interrupt.
182+
*
183+
* Requires enabling global interrupts (EA=1) separately.
184+
*
185+
* The USART interrupt fires for both *receive* (RX) and *transmit* (TX)
186+
* completing, the interrupt must clear *both*.
187+
**/
188+
#define ENABLE_USART0() \
189+
ES0 = 1;
190+
/**
191+
* \brief Clear USART 0 RX bit.
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**/
115-
#define CLEAR_INT5() EXIF &= ~0x80
193+
#define CLEAR_USART0_RX() \
194+
RI = 0;
195+
/**
196+
* \brief Clear USART 0 TX bit.
197+
**/
198+
#define CLEAR_USART0_TX() \
199+
TI = 0;
200+
/**
201+
* \brief Clear USART 0 both TX & RX bit.
202+
**/
203+
#define CLEAR_USART0() \
204+
CLEAR_USART0_RX(); \
205+
CLEAR_USART0_TX();
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207+
// USART1
208+
// =======================================================================
209+
210+
/**
211+
* \brief Set the USART 1 interrupt priority.
212+
*
213+
* Does *not* enable the interrupt.
214+
*
215+
* \code
216+
* SET_USART1_ISR_PRIO(INTERRUPT_HIGH_PRIO); // Set USART1 to high priority
217+
* SET_USART1_ISR_PRIO(INTERRUPT_LOW_PRIO); // Set USART1 to low priority
218+
* \endcode
219+
**/
220+
#define SET_USART1_ISR_PRIORITY(p) \
221+
PS1 = p
222+
/**
223+
* \brief Enable the USART 1 interrupt.
224+
*
225+
* Requires enabling global interrupts (EA=1) separately.
226+
*
227+
* The USART interrupt fires for both *receive* (RX) and *transmit* (TX)
228+
* completing, the interrupt must clear *both*.
229+
**/
230+
#define ENABLE_USART1() \
231+
ES1 = 1;
232+
/**
233+
* \brief Clear USART 1 receive (RI1) bit.
234+
**/
235+
#define CLEAR_USART1_RX() \
236+
RI1 = 0;
237+
/**
238+
* \brief Clear USART 1 transmit (TI1) bit.
239+
**/
240+
#define CLEAR_USART1_TX() \
241+
TI1 = 0;
242+
/**
243+
* \brief Clear USART 1 both TX & RX bits.
244+
**/
245+
#define CLEAR_USART1() \
246+
CLEAR_USART1_RX(); \
247+
CLEAR_USART1_TX();
248+
249+
// I2C Interrupt
250+
// =======================================================================
251+
252+
/**
253+
* \brief Set the I2C interrupt priority.
254+
*
255+
* Does *not* enable the interrupt.
256+
*
257+
* \code
258+
* SET_I2C_ISR_PRIO(INTERRUPT_HIGH_PRIO) // Set I2C to high priority
259+
* SET_I2C_ISR_PRIO(INTERRUPT_LOW_PRIO) // Set I2C to low priority
260+
* \endcode
261+
**/
262+
#define SET_I2C_ISR_PRIORITY(p) \
263+
PI2C = p
264+
/**
265+
* \brief Enable the I2C interrupt.
266+
*
267+
* Requires enabling global interrupts (EA=1) separately.
268+
*
269+
* The USART interrupt fires for both *receive* (RX) and *transmit* (TX)
270+
* completing, the interrupt must clear *both*.
271+
**/
272+
#define ENABLE_I2C() \
273+
EI2C = 1;
274+
/**
275+
* \brief Clear I2C interrupt.
276+
**/
277+
#define CLEAR_I2C() \
278+
EXIF &= ~bmI2CINT;

‎include/fx2regs.h‎

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@@ -635,4 +635,10 @@ __sfr __at 0xF8 EIP; // EIP Bit Values differ from Reg320
635635
#define bmEP1OUTBSY bmBIT1
636636
#define bmEP0BSY bmBIT0
637637

638+
/* EXIF - External interrupt flags */
639+
#define bmIE5 bmBIT7
640+
#define bmIE4 bmBIT6
641+
#define bmI2CINT bmBIT5
642+
#define bmUSBNT bmBIT4
643+
638644
#endif /* FX2REGS_H */

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