astil_forth/forth/simd.af at main · mitranim/astil_forth · GitHub

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use' ./lang.af

\ BOT-ASSISTED

\ ld1 {Vt.16b}, [Xn]
fun: asm_ld1_16b { Vt Xn -> instr }
  5 .lsl .or 0b01001100010_00000_011100_00000_00000 .or
end

\ movi Vd.16b, #imm8
fun: asm_movi_16b { Vd imm8 -- instr }
  imm8 31  .and 5  .lsl { low }
  imm8 224 .and 11 .lsl { high }
  Vd low .or high .or 0b01001111000_00000_111001_00000_00000 .or
end

\ movi Vd.2d, #0
fun: asm_movi_2d_zero { Vd -> instr }
  0b0_11_01111_00_0_00000_111001_00000_00000 .or
end

\ Shared by 3-vector ops.
fun: asm_pattern_vec3_16b { Vd Vn Vm -- instr_mask }
  Vd Vn 5 .lsl .or Vm 16 .lsl .or
end

\ cmeq Vd.16b, Vn.16b, Vm.16b
fun: asm_cmeq_16b { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_11_01110_00_1_00000_100011_00000_00000 .or
end

\ orr Vd.16b, Vn.16b, Vm.16b
fun: asm_orr_16b { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_10_01110_10_1_00000_000111_00000_00000 .or
end

\ and Vd.16b, Vn.16b, Vm.16b
fun: asm_and_16b { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_10_01110_00_1_00000_000111_00000_00000 .or
end

\ add Vd.16b, Vn.16b, Vm.16b
fun: asm_add_16b { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_10_01110_00_1_00000_100001_00000_00000 .or
end

\ cmhi Vd.16b, Vn.16b, Vm.16b
fun: asm_cmhi_16b { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_11_01110_00_1_00000_001101_00000_00000 .or
end

\ addv Bd, Vn.16b
fun: asm_addv_16b { Bd Vn -> instr }
  5 .lsl .or 0b0_1_0_01110_00_11000_11011_10_00000_00000 .or
end

\ uaddlp Vd.8h, Vn.16b
fun: asm_uaddlp_8h { Vd Vn -> instr }
  5 .lsl .or 0b0_11_01110_00_1_00000_001010_00000_00000 .or
end

\ uaddw Vd.8h, Vn.8h, Vm.8b
fun: asm_uaddw_8h { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_01_01110_00_1_00000_000100_00000_00000 .or
end

\ uaddw2 Vd.8h, Vn.8h, Vm.16b
fun: asm_uaddw2_8h { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_11_01110_00_1_00000_000100_00000_00000 .or
end

\ uaddlp Vd.4s, Vn.8h
fun: asm_uaddlp_4s { Vd Vn -> instr }
  5 .lsl .or 0b0_11_01110_01_1_00000_001010_00000_00000 .or
end

\ uaddlp Vd.2d, Vn.4s
fun: asm_uaddlp_2d { Vd Vn -> instr }
  5 .lsl .or 0b0_11_01110_10_1_00000_001010_00000_00000 .or
end

\ add Vd.2d, Vn.2d, Vm.2d
fun: asm_add_2d { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_10_01110_11_1_00000_100001_00000_00000 .or
end

\ addp Vd.2d, Vn.2d, Vm.2d
fun: asm_addp_2d { Vd Vn Vm -> instr }
  .asm_pattern_vec3_16b 0b0_10_01110_11_1_00000_101111_00000_00000 .or
end

\ umov Wd, Vn.b[0]
fun: asm_umov_b0 { Wd Vn -> instr }
  5 .lsl .or 0b0_0_0_01110_000_00001_001111_00000_00000 .or
end

\ umov Xd, Vn.d[0]
fun: asm_umov_d0 { Xd Vn -> instr }
  5 .lsl .or 0b0_10_01110_00_0_01000_001111_00000_00000 .or
end

\ Set `Vmask.16b` to `(Vsrc == Va) | (Vsrc == Vb)`.
fun: comp_cmeq_pair_mask_16b { Vmask Vtmp Vsrc Va Vb -- err }
  Vtmp  Vsrc  Va   .asm_cmeq_16b .comp_instr \ cmeq Vtmp.16b, Vsrc.16b, Va.16b
  Vmask Vsrc  Vb   .asm_cmeq_16b .comp_instr \ cmeq Vmask.16b, Vsrc.16b, Vb.16b
  Vmask Vmask Vtmp .asm_orr_16b  .comp_instr \ orr  Vmask.16b, Vmask.16b, Vtmp.16b
end

\ OR `(Vsrc == Vconst)` into `Vmask.16b`.
fun: comp_cmeq_or_mask_16b { Vmask Vtmp Vsrc Vconst -- err }
  Vtmp  Vsrc  Vconst .asm_cmeq_16b .comp_instr \ cmeq Vtmp.16b, Vsrc.16b, Vconst.16b
  Vmask Vmask Vtmp   .asm_orr_16b  .comp_instr \ orr  Vmask.16b, Vmask.16b, Vtmp.16b
end

\ Set `Vdst.16b` to `Vsrc.16b` in byte range [`-Vbias`, `-Vbias + Vlimit`).
fun: comp_u8_range_mask_16b { Vdst Vsrc Vbias Vlimit -- err }
  Vdst Vsrc   Vbias .asm_add_16b  .comp_instr \ add  Vdst.16b, Vsrc.16b, Vbias.16b
  Vdst Vlimit Vdst  .asm_cmhi_16b .comp_instr \ cmhi Vdst.16b, Vlimit.16b, Vdst.16b
end

\ Convert all-ones/all-zero predicate bytes to 1/0 byte lanes.
fun: comp_mask_to_u8_lanes_16b { Vmask Vone -- err }
  Vmask Vmask Vone .asm_and_16b .comp_instr \ and Vmask.16b, Vmask.16b, Vone.16b
end

\ Accumulate byte counts from 0/1 lanes in `Vmask.16b` into two `8h` accumulators.
fun: comp_u8x16_counts_accum { Vlow Vhigh Vmask -- err }
  Vlow  Vlow  Vmask .asm_uaddw_8h  .comp_instr \ uaddw Vlow.8h, Vlow.8h, Vmask.8b
  Vhigh Vhigh Vmask .asm_uaddw2_8h .comp_instr \ uaddw2 Vhigh.8h, Vhigh.8h, Vmask.16b
end

\ Horizontally sum paired `8h` accumulators into `Xd`.
fun: comp_u16x8_pair_sum_umov_d0 { Xd Vlow Vhigh -- err }
  Vlow  Vlow        .asm_uaddlp_4s .comp_instr \ uaddlp Vlow.4s, Vlow.8h
  Vhigh Vhigh       .asm_uaddlp_4s .comp_instr \ uaddlp Vhigh.4s, Vhigh.8h
  Vlow  Vlow        .asm_uaddlp_2d .comp_instr \ uaddlp Vlow.2d, Vlow.4s
  Vhigh Vhigh       .asm_uaddlp_2d .comp_instr \ uaddlp Vhigh.2d, Vhigh.4s
  Vlow  Vlow  Vhigh .asm_add_2d    .comp_instr \ add Vlow.2d, Vlow.2d, Vhigh.2d
  Vlow  Vlow  Vlow  .asm_addp_2d   .comp_instr \ addp Vlow.2d, Vlow.2d, Vlow.2d
  Xd    Vlow        .asm_umov_d0   .comp_instr \ umov Xd, Vlow.d[0]
end