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mkeetermkeeter
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Add register repacking
1 parent 1735e79 commit d9a7a29

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‎CHANGELOG.md‎

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Original file line numberDiff line numberDiff line change
@@ -33,6 +33,11 @@
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code using `anyhow` (or similar) may not need to change
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- Fix a bug in bulk evaluator argument checks where mismatched slices could be
3535
allowed under some circumstances
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- Add `VmData::asm` to get an immutable reference to the inner `RegTape`
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- Add `RegTape::repack_map` and `RegTape::repack` to repack registers by
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frequency (making register 0 the most frequently used, etc)
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- Add `RegOp::visit_regs` and `RegOp::visit_regs_mut` to visit registers in an
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operation
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# 0.4.3
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- Fixed bug in x86 interval `OR` function ([#395](https://github.com/mkeeter/fidget/pull/395)),

‎fidget-bytecode/src/lib.rs‎

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@@ -193,6 +193,8 @@ impl Bytecode {
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pub fn new<const N: usize>(
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t: &VmData<N>,
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) -> Result<Self, ReservedRegister> {
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// Build a map for repacking registers by frequency
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let map = t.asm().repack_map();
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// The initial opcode is `OP_JUMP 0x0000_0000`
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let mut data = vec![u32::MAX, 0u32];
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let mut reg_count = 0u8;
@@ -205,6 +207,7 @@ impl Bytecode {
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if r == u8::MAX {
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Err(ReservedRegister)
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} else {
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let r = map[&r];
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reg_count = reg_count.max(r + 1);
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word[i] = r;
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Ok(())

‎fidget-core/src/compiler/op.rs‎

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@@ -288,3 +288,214 @@ opcodes!(
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Store(u8, u32),
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}
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);
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impl RegOp {
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/// Returns the output register (if present)
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pub fn output(&self) -> Option<u8> {
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match self {
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RegOp::Input(out, ..)
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| RegOp::CopyImm(out, ..)
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| RegOp::NegReg(out, ..)
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| RegOp::AbsReg(out, ..)
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| RegOp::RecipReg(out, ..)
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| RegOp::SqrtReg(out, ..)
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| RegOp::SquareReg(out, ..)
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| RegOp::FloorReg(out, ..)
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| RegOp::CeilReg(out, ..)
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| RegOp::RoundReg(out, ..)
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| RegOp::CopyReg(out, ..)
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| RegOp::SinReg(out, ..)
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| RegOp::CosReg(out, ..)
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| RegOp::TanReg(out, ..)
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| RegOp::AsinReg(out, ..)
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| RegOp::AcosReg(out, ..)
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| RegOp::AtanReg(out, ..)
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| RegOp::ExpReg(out, ..)
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| RegOp::LnReg(out, ..)
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| RegOp::NotReg(out, ..)
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| RegOp::AddRegImm(out, ..)
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| RegOp::MulRegImm(out, ..)
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| RegOp::DivRegImm(out, ..)
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| RegOp::DivImmReg(out, ..)
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| RegOp::SubImmReg(out, ..)
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| RegOp::SubRegImm(out, ..)
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| RegOp::AddRegReg(out, ..)
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| RegOp::MulRegReg(out, ..)
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| RegOp::DivRegReg(out, ..)
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| RegOp::SubRegReg(out, ..)
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| RegOp::AtanRegReg(out, ..)
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| RegOp::AtanRegImm(out, ..)
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| RegOp::AtanImmReg(out, ..)
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| RegOp::MinRegImm(out, ..)
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| RegOp::MaxRegImm(out, ..)
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| RegOp::MinRegReg(out, ..)
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| RegOp::MaxRegReg(out, ..)
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| RegOp::CompareRegReg(out, ..)
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| RegOp::CompareRegImm(out, ..)
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| RegOp::CompareImmReg(out, ..)
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| RegOp::ModRegReg(out, ..)
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| RegOp::ModRegImm(out, ..)
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| RegOp::ModImmReg(out, ..)
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| RegOp::AndRegImm(out, ..)
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| RegOp::AndRegReg(out, ..)
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| RegOp::OrRegImm(out, ..)
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| RegOp::OrRegReg(out, ..)
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| RegOp::Load(out, ..) => Some(*out),
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RegOp::Output(..) | RegOp::Store(..) => None,
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}
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}
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/// Apply a mutating function to every register in the op
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///
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/// Both inputs and outputs are visited
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pub fn visit_regs_mut<F: FnMut(&mut u8)>(&mut self, mut f: F) {
352+
match self {
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RegOp::CopyImm(out, imm) => {
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let _: f32 = *imm;
355+
f(out)
356+
}
357+
RegOp::NegReg(out, arg)
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| RegOp::AbsReg(out, arg)
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| RegOp::RecipReg(out, arg)
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| RegOp::SqrtReg(out, arg)
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| RegOp::SquareReg(out, arg)
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| RegOp::FloorReg(out, arg)
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| RegOp::CeilReg(out, arg)
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| RegOp::RoundReg(out, arg)
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| RegOp::CopyReg(out, arg)
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| RegOp::SinReg(out, arg)
367+
| RegOp::CosReg(out, arg)
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| RegOp::TanReg(out, arg)
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| RegOp::AsinReg(out, arg)
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| RegOp::AcosReg(out, arg)
371+
| RegOp::AtanReg(out, arg)
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| RegOp::ExpReg(out, arg)
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| RegOp::LnReg(out, arg)
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| RegOp::NotReg(out, arg) => {
375+
f(out);
376+
f(arg);
377+
}
378+
RegOp::AddRegImm(out, arg, imm)
379+
| RegOp::MulRegImm(out, arg, imm)
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| RegOp::DivRegImm(out, arg, imm)
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| RegOp::DivImmReg(out, arg, imm)
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| RegOp::SubImmReg(out, arg, imm)
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| RegOp::SubRegImm(out, arg, imm)
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| RegOp::AtanRegImm(out, arg, imm)
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| RegOp::AtanImmReg(out, arg, imm)
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| RegOp::MinRegImm(out, arg, imm)
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| RegOp::MaxRegImm(out, arg, imm)
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| RegOp::CompareRegImm(out, arg, imm)
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| RegOp::CompareImmReg(out, arg, imm)
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| RegOp::ModRegImm(out, arg, imm)
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| RegOp::ModImmReg(out, arg, imm)
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| RegOp::AndRegImm(out, arg, imm)
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| RegOp::OrRegImm(out, arg, imm) => {
394+
let _: f32 = *imm; // type-checking pattern
395+
f(out);
396+
f(arg);
397+
}
398+
399+
RegOp::AddRegReg(out, lhs, rhs)
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| RegOp::MulRegReg(out, lhs, rhs)
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| RegOp::DivRegReg(out, lhs, rhs)
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| RegOp::SubRegReg(out, lhs, rhs)
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| RegOp::AtanRegReg(out, lhs, rhs)
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| RegOp::MinRegReg(out, lhs, rhs)
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| RegOp::MaxRegReg(out, lhs, rhs)
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| RegOp::CompareRegReg(out, lhs, rhs)
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| RegOp::ModRegReg(out, lhs, rhs)
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| RegOp::AndRegReg(out, lhs, rhs)
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| RegOp::OrRegReg(out, lhs, rhs) => {
410+
f(out);
411+
f(lhs);
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f(rhs);
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}
414+
415+
RegOp::Output(reg, imm)
416+
| RegOp::Input(reg, imm)
417+
| RegOp::Store(reg, imm)
418+
| RegOp::Load(reg, imm) => {
419+
let _: u32 = *imm; // type-checking pattern
420+
f(reg)
421+
}
422+
}
423+
}
424+
425+
/// Apply a function to every register in the op
426+
///
427+
/// Both inputs and outputs are visited
428+
pub fn visit_regs<F: FnMut(u8)>(&self, mut f: F) {
429+
match self {
430+
RegOp::CopyImm(out, imm) => {
431+
let _: f32 = *imm;
432+
f(*out)
433+
}
434+
RegOp::NegReg(out, arg)
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| RegOp::AbsReg(out, arg)
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| RegOp::RecipReg(out, arg)
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| RegOp::SqrtReg(out, arg)
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| RegOp::SquareReg(out, arg)
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| RegOp::FloorReg(out, arg)
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| RegOp::CeilReg(out, arg)
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| RegOp::RoundReg(out, arg)
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| RegOp::CopyReg(out, arg)
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| RegOp::SinReg(out, arg)
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| RegOp::CosReg(out, arg)
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| RegOp::TanReg(out, arg)
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| RegOp::AsinReg(out, arg)
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| RegOp::AcosReg(out, arg)
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| RegOp::AtanReg(out, arg)
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| RegOp::ExpReg(out, arg)
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| RegOp::LnReg(out, arg)
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| RegOp::NotReg(out, arg) => {
452+
f(*out);
453+
f(*arg);
454+
}
455+
RegOp::AddRegImm(out, arg, imm)
456+
| RegOp::MulRegImm(out, arg, imm)
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| RegOp::DivRegImm(out, arg, imm)
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| RegOp::DivImmReg(out, arg, imm)
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| RegOp::SubImmReg(out, arg, imm)
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| RegOp::SubRegImm(out, arg, imm)
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| RegOp::AtanRegImm(out, arg, imm)
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| RegOp::AtanImmReg(out, arg, imm)
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| RegOp::MinRegImm(out, arg, imm)
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| RegOp::MaxRegImm(out, arg, imm)
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| RegOp::CompareRegImm(out, arg, imm)
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| RegOp::CompareImmReg(out, arg, imm)
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| RegOp::ModRegImm(out, arg, imm)
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| RegOp::ModImmReg(out, arg, imm)
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| RegOp::AndRegImm(out, arg, imm)
470+
| RegOp::OrRegImm(out, arg, imm) => {
471+
let _: f32 = *imm; // type-checking pattern
472+
f(*out);
473+
f(*arg);
474+
}
475+
476+
RegOp::AddRegReg(out, lhs, rhs)
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| RegOp::MulRegReg(out, lhs, rhs)
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| RegOp::DivRegReg(out, lhs, rhs)
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| RegOp::SubRegReg(out, lhs, rhs)
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| RegOp::AtanRegReg(out, lhs, rhs)
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| RegOp::MinRegReg(out, lhs, rhs)
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| RegOp::MaxRegReg(out, lhs, rhs)
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| RegOp::CompareRegReg(out, lhs, rhs)
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| RegOp::ModRegReg(out, lhs, rhs)
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| RegOp::AndRegReg(out, lhs, rhs)
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| RegOp::OrRegReg(out, lhs, rhs) => {
487+
f(*out);
488+
f(*lhs);
489+
f(*rhs);
490+
}
491+
492+
RegOp::Output(reg, imm)
493+
| RegOp::Input(reg, imm)
494+
| RegOp::Store(reg, imm)
495+
| RegOp::Load(reg, imm) => {
496+
let _: u32 = *imm; // type-checking pattern
497+
f(*reg)
498+
}
499+
}
500+
}
501+
}

‎fidget-core/src/compiler/reg_tape.rs‎

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Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
//! Tape used for evaluation
22
use crate::compiler::{RegOp, RegisterAllocator, SsaTape};
33
use serde::{Deserialize, Serialize};
4+
use std::collections::HashMap;
45

56
/// Low-level tape for use with the Fidget virtual machine (or to be lowered
67
/// further into machine instructions).
@@ -9,6 +10,9 @@ pub struct RegTape {
910
tape: Vec<RegOp>,
1011

1112
/// Total allocated slots
13+
///
14+
/// This is a continuous space of registers (`0..N`) and memory (`N..`),
15+
/// where `N` is the parameter in [`RegTape::new`].
1216
pub(super) slot_count: u32,
1317
}
1418

@@ -27,6 +31,35 @@ impl RegTape {
2731
alloc.finalize()
2832
}
2933

34+
/// Repacks registers by frequency (so that register 0 is the most frequent)
35+
pub fn repack(&mut self) {
36+
let map = self.repack_map();
37+
for op in &mut self.tape {
38+
op.visit_regs_mut(|reg| *reg = map[reg]);
39+
}
40+
}
41+
42+
/// Returns a map for register repacking
43+
///
44+
/// The map repacks registers in the tape by frequency, so that register 0
45+
/// is the most frequent.
46+
pub fn repack_map(&self) -> HashMap<u8, u8> {
47+
let mut reg_counts: HashMap<u8, usize> = HashMap::new();
48+
for op in &self.tape {
49+
op.visit_regs(|reg| *reg_counts.entry(reg).or_default() += 1);
50+
}
51+
let mut sorted = reg_counts
52+
.into_iter()
53+
.map(|(reg, count)| (std::cmp::Reverse(count), reg))
54+
.collect::<Vec<_>>();
55+
sorted.sort_unstable();
56+
sorted
57+
.into_iter()
58+
.enumerate()
59+
.map(|(i, (_count, reg))| (reg, u8::try_from(i).unwrap()))
60+
.collect()
61+
}
62+
3063
/// Builds a new empty tape
3164
pub(crate) fn empty() -> Self {
3265
Self {

‎fidget-core/src/vm/data.rs‎

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@@ -318,6 +318,11 @@ impl<const N: usize> VmData<N> {
318318
self.asm.iter().cloned().rev()
319319
}
320320

321+
/// Returns a reference to the inner [`RegTape`]
322+
pub fn asm(&self) -> &RegTape {
323+
&self.asm
324+
}
325+
321326
/// Pretty-prints the inner SSA tape
322327
pub fn pretty_print(&self) {
323328
self.ssa.pretty_print();

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