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docs(readme): document 0.5.0 feature additions
Add coverage for features shipped in 0.5.0: - Fused GEMM epilogue (matmul+bias+activation, forward+backward) - Fused activation-mul for gated architectures - Fused add-norm (residual + normalize in one pass) - Fused element-wise operation chains across all backends - i8×i8→i32 and FP8 quantized matmul paths - 2:4 structured sparsity with multi-backend support - slice_assign indexing operation - Seeded deterministic RNG - Expanded autograd differentiable op coverage - CUDA caching allocator and GEMV fast paths
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README.md

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@@ -90,7 +90,7 @@ numr implements a comprehensive set of tensor operations across CPU, CUDA, and W
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### Shape and Data Movement
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- **ShapeOps**: cat, stack, split, chunk, repeat, pad, roll
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- **IndexingOps**: gather, scatter, gather_nd, scatter_reduce, index_select, masked_select, masked_fill, embedding_lookup, bincount, argmax, argmin
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- **IndexingOps**: gather, scatter, gather_nd, scatter_reduce, index_select, masked_select, masked_fill, embedding_lookup, bincount, argmax, argmin, slice_assign
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- **SortingOps**: sort, argsort, topk, unique, nonzero, searchsorted
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### Reductions
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### Activation & Normalization Functions
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- **ActivationOps**: relu, sigmoid, silu, gelu, swiglu, leaky_relu, elu, softmax, dropout
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- **NormalizationOps**: rms_norm, layer_norm, batch_norm, group_norm, instance_norm
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- **ActivationOps**: relu, sigmoid, silu, gelu, swiglu, leaky_relu, elu, softmax, dropout, fused activation-mul (for gated architectures)
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- **NormalizationOps**: rms_norm, layer_norm, batch_norm, group_norm, instance_norm, fused add-norm (residual + normalize in one pass)
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- **GemmEpilogueOps**: fused matmul+bias+activation in a single kernel (forward + backward)
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- **FusedElementwiseOps**: fused element-wise operation chains across all backends
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- **ConvOps**: conv1d, conv2d, depthwise_conv2d (with stride, padding, dilation, groups)
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- **EinsumOps**: Einstein summation notation
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_These are mathematical functions commonly used in ML, but numr itself is not an ML framework._
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### Linear Algebra
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- **MatmulOps**: matmul, matmul_bias (fused GEMM+bias)
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- **MatmulOps**: matmul, matmul_bias (fused GEMM+bias), i8×i8→i32 quantized matmul, FP8 matmul
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- **LinalgOps**: solve, lstsq, pinverse, inverse, det, trace, matrix_rank, diag, matrix_norm, kron, khatri_rao
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- **ComplexOps**: conj, real, imag, angle (for complex tensor support)
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- **Second-order**: `hvp()` for Hessian-vector products, `backward_with_graph()` for higher-order gradients
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- **Activation checkpointing**: `checkpoint()` to trade compute for memory
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- **Backward hooks**: `BackwardHook` trait for gradient notifications (e.g., distributed allreduce)
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- **Differentiable ops**: matmul, conv1d, conv2d, softmax, rms_norm, layer_norm, SiLU, softplus, SwiGLU, dropout, fused GEMM epilogue, fused add-norm, dtype cast, narrow, cat
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### Statistics and Probability
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- **StatisticalOps**: var, std, skew, kurtosis, quantile, percentile, median, cov, corrcoef
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- **RandomOps**: rand, randn, randint, multinomial, bernoulli, poisson, binomial, beta, gamma, exponential, chi_squared, student_t, f_distribution
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- **RandomOps**: rand, randn, randint, multinomial, bernoulli, poisson, binomial, beta, gamma, exponential, chi_squared, student_t, f_distribution (with seeded deterministic generation)
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- **MultivariateRandomOps**: multivariate_normal, wishart, dirichlet
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- **QuasirandomOps**: Sobol, Halton sequences
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- Formats: CSR, CSC, COO
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- Operations: SpGEMM (sparse matrix multiplication), SpMV (sparse matrix-vector), DSMM (dense-sparse matrix)
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- 2:4 structured sparsity with multi-backend support
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**Sparse Linear Algebra (`numr::sparse_linalg`):**
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All backends implement identical algorithms with native kernels—no cuBLAS, MKL, or vendor library dependencies.
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| Hardware | Backend | Feature | Status | Notes |
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| ------------ | ------- | ------------- | ------- | ------------------ |
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| CPU (x86-64) | CPU | cpu (default) || AVX-512/AVX2 SIMD |
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| CPU (ARM64) | CPU | cpu || NEON SIMD |
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| NVIDIA GPU | CUDA | cuda || Native PTX kernels |
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| AMD GPU | WebGPU | wgpu || WGSL shaders |
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| Intel GPU | WebGPU | wgpu || WGSL shaders |
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| Apple GPU | WebGPU | wgpu || WGSL shaders |
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| AMD GPU | ROCm | - | Planned | Native HIP kernels |
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| Hardware | Backend | Feature | Status | Notes |
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| ------------ | ------- | ------------- | ------- | ------------------------------------------------------ |
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| CPU (x86-64) | CPU | cpu (default) || AVX-512/AVX2 SIMD |
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| CPU (ARM64) | CPU | cpu || NEON SIMD |
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| NVIDIA GPU | CUDA | cuda || Native PTX kernels, caching allocator, GEMV fast paths |
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| AMD GPU | WebGPU | wgpu || WGSL shaders |
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| Intel GPU | WebGPU | wgpu || WGSL shaders |
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| Apple GPU | WebGPU | wgpu || WGSL shaders |
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| AMD GPU | ROCm | - | Planned | Native HIP kernels |
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### SIMD Acceleration
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