feat(languages): add vhdl (@joelievt)

[joelievt]

Description

Adds VHDL. There's already SystemVerilog, so this completes the big HDL pair. Word list is IEEE 1076-2008 reserved words plus a few stdlib identifiers.

Also added some quotes, which are listings from Free Range VHDL.

Checks

• Adding quotes?
  • Make sure to include translations for the quotes in the description (or another comment) so we can verify their content.
    • (Not needed?)
• Adding a language?
  • Add language to packages/schemas/src/languages.ts
  • Add language to exactly one group in frontend/src/ts/constants/languages.ts
  • Add language json file to frontend/static/languages
• Check if any open issues are related to this PR; if so, be sure to tag them below.
  • None
• Make sure the PR title follows the Conventional Commits standard. (https://www.conventionalcommits.org for more info)
• Make sure to include your GitHub username prefixed with @ inside parentheses at the end of the PR title.

[Leonabcd123]

Per the languages documentation:

"Go to packages/schemas/src/languages.ts and add your new language name at the end of the LanguageSchema enum."

Please move it to the end of the enum (also move it to the end of the code group in frontend/src/ts/constants/languages.ts).

[joelievt]

Done!