Bug 2008779 - Fix memory leak in AboutPageAdapter#31
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"fenix-detect-leaks" try: https://treeherder.mozilla.org/jobs?repo=try&landoCommitID=173591 Pull request: #31
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"fenix-detect-leaks" try: https://treeherder.mozilla.org/jobs?repo=try&landoCommitID=173591 Pull request: mozilla-firefox/firefox#31
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…est + ma_*TestCarry
Audit-driven cleanup of redundant scratch-acquires and dead instructions
across several helper families. All fixes share the same theme:
identify a GPR scratch that's allocated for a single-use intermediate
when the same operation can be done in-place or via a pre-existing
delegation.
Concretely:
(1) branchMul32: scratch is dead after `mulld dest, dest, scratch`
(consumed as RB), so the sign-extension round-trip reuses it instead
of acquiring a second scratch.
(2) branchTest32(Address, Imm32) / branchTest32(AbsoluteAddress, Imm32) /
branchTestPtr(Address, Imm32) / test32MovePtr: previously had inline
"if (16-bit-fit) andi. else { scratch2 + move + and_ }". Replaced with
a direct call to and32/andPtr, which already has the rlwinm
contiguous-mask fast path (item mozilla-firefox#16/mozilla-firefox#17 in PLAN.md) for tag-mask /
header-bitfield immediates that aren't 16-bit-fit but are contig
runs. Also folds the trailing extsw inside and32.
(3) loadUnalignedSimd128(BaseIndex) / storeUnalignedSimd128(BaseIndex) /
loadDouble(BaseIndex) / loadFloat32(BaseIndex) /
store{8,16,32,Ptr}(BaseIndex) non-fitting-offset paths: previously
all had `Register scratch2 = temps.Acquire(); movePtr(ImmWord(offset),
scratch2); stXx(src, scratch, scratch2)` (or load equivalent). The
addPtr(ImmWord, Register) helper already picks up POWER10 paddi (1
prefixed insn) when the offset fits 34-bit signed, falling back to
the same movePtr+add on P9/P8. So we just `addPtr(ImmWord(offset),
scratch); stX(src, scratch, 0)` (D-form with 0 displacement, or
stdx(src, r0, scratch) for stdptr to keep alignment-agnostic). Drops
scratch2 acquire entirely and shrinks the offset emit on POWER10
from 2 insns to 1.
(4) ma_add32TestCarry: cmplw compares only the low 32 bits as
unsigned, so the explicit `rldicl ..., 0, 32` zero-extends on rs and
rd were dead. Drop them along with the scratch they needed; just
move32 + add32 + cmplw + ma_b.
(5) ma_addPtrTestCarry: rs is preserved by addPtr (which writes only
rd), so when rd != rs we can compare result vs rs directly without
saving rs to a scratch first. The rd == rs case still needs the
scratch since addPtr clobbers the input — split into two paths.
PLAN.md items mozilla-firefox#19, mozilla-firefox#20 superseded by these; remaining items mozilla-firefox#29-mozilla-firefox#31
(POWER10 prefixed-load/store family) still standalone wins.
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…2/loadUnalignedSimd128 (Address) Adds a HasPOWER10()+34-bit-signed-offset fast path before the movePtr+indexed-load fallback in: - loadPtr(Address) → as_pld - loadDouble(Address) → as_plfd - loadFloat32(Address) → as_plfs - loadUnalignedSimd128(Address) → as_plxv Each replaces the 2-insn `movePtr scratch + lXdx` sequence (plus a GPR scratch acquire) with a single 8-byte prefixed load when the offset fits 34-bit signed. Hot on deep stack frames where slot offsets exceed 16-bit signed (loadPtr) and on FP/SIMD reads from constant-offset structure fields. The DS-form (loadPtr) and 16-bit- signed (loadDouble/Float32) fast paths are still preferred when applicable — they're 4 bytes vs 8 for the prefixed form. All four emitters (`as_pld` / `as_plfd` / `as_plfs` / `as_plxv`) were already wired and used elsewhere; this commit only plumbs them into the Address-form load helpers. Verified across the verification matrix: - Real-P9 (`obj-sm-dbgopt`): wasm/large-memory + wasm/memory + wasm/spec/spec/address + ion + basic 3958/0 - Real-P10 (`power10`): same suite 3958/0 - ARM64 sim FORCE_POWER10: same suite 3958/0 Closes PLAN.md candidates mozilla-firefox#19 (read-side), mozilla-firefox#29, mozilla-firefox#30. Item mozilla-firefox#31 (prefixed-store side) still pending — it needs new emitters (as_pstd/as_pstfd/as_pstfs/as_pstxv) and matching sim decoders.
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…e/storeFloat32/storeUnalignedSimd128 (Address) Adds the four prefixed-store emitters that mirror the existing prefixed-load family: - as_pstd (8LS prefix, suffix opcode 61) - as_pstxv (8LS prefix, 5-bit suffix opcode 27 + SX bit) - as_pstfd (MLS prefix, suffix opcode 54) - as_pstfs (MLS prefix, suffix opcode 52) Encodings empirically verified against `gcc -mcpu=power10 -c` + objdump on the power10 box (suffix opcode for pstd is 61, not 62 of the DS-form std — pstd is the D-form variant introduced in ISA 3.1). Matching sim decoders added in decodePrefixed (type=0/suffixOp6=61 pstd, type=2/suffixOp6=54 pstfd, type=2/suffixOp6=52 pstfs, type=0/suffixOp5=27 pstxv). Plumbed into the four Address-form store helpers as a HasPOWER10() fast path before the movePtr+indexed-store fallback, mirroring the load-side fast paths shipped in d67b3db: - storePtr (DS-form preferred when applicable) - storeDouble / storeFloat32 (16-bit-signed direct preferred) - storeUnalignedSimd128 (P10 path inserted ahead of P9 lxvx + P8 stxvd2x) Saves the GPR scratch acquire and one insn in each call when the offset is 17–34 bit signed. Verified across the matrix: - Real-P9 (`obj-sm-dbgopt`): wasm/large-memory + wasm/memory + wasm/spec/spec/address + ion + basic 3958/0 (HasPOWER10=false, paths inactive — confirms no regression in shared code). - Real-P10 (`power10`): same suite 3958/0 (P10 paths active). - ARM64 sim FORCE_POWER10: same suite 3958/0 (sim decoders active). Closes PLAN.md candidate mozilla-firefox#31. The corresponding load-side wins (mozilla-firefox#19, mozilla-firefox#29, mozilla-firefox#30) shipped earlier in d67b3db.
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…a-firefox#29/mozilla-firefox#30/mozilla-firefox#31 DONE Load-side (mozilla-firefox#19 read, mozilla-firefox#29, mozilla-firefox#30) shipped in d67b3db; store-side (mozilla-firefox#19 write, mozilla-firefox#31) shipped in 5309082 with new pstd/pstxv/pstfd/ pstfs emitters and matching sim decoders. All four sites verified across real-P9 + real-P10 + sim FORCE_POWER10.
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…jandem To avoid repeating the same optimisations across all architectures, handle these comparisons at the MIR level. 1. `i >= 1` Before: x86 ```asm cmpl $0x1, %eax jl ``` arm64 ```asm cmp w0, #0x1 b.lt ``` riscv64 ```asm li t4, 1 bge t0, t4, 0 nop auipc t4, 0x0 jr t4 ``` Now: x86 ```asm testl %eax, %eax jle ``` arm64 (no optimisation!): ```asm cmp w0, #0x0 b.le ``` riscv64: ```asm blt zero, t0, 0 nop auipc t4, 0x0 jr t4 ``` 2. Changes for `i < 1` are similar to `i >= 1`. 3. `i <= -1` Before: x86 ```asm cmpl $0xffffffff, %eax jg ``` arm64 ```asm cmn w0, #0x1 b.gt ``` riscv64 ```asm li t4, -1 bge t4, t0, 0 nop auipc t4, 0x0 jr t4 ``` Now: x86 ```asm testl %eax, %eax jge ``` arm64 ```asm tbz w0, #31 ``` riscv64 ```asm blt t0, zero, 0 nop auipc t4, 0x0 jr t4 ``` 4. Changes for `i > -1` are similar to `i <= -1`. Differential Revision: https://phabricator.services.mozilla.com/D297325
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"fenix-detect-leaks" try: https://treeherder.mozilla.org/jobs?repo=try&landoCommitID=173591