The Xctcmsg RISC-V extension defines a set of instructions that allows the harts in a manycore system to communicate with one another with messages. This repository contains the reference design of a functional unit implementing the extension.
- Design and Implementation of a RISC-V ISA Extension for Direct Core-to-Core Message Communication (undergraduate thesis, 2025): https://hdl.handle.net/2117/449222
To be done
This project is licensed under the Solderpad Hardware License - see the LICENSE file for details.