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Fix alcatel_sros sh lag when there are lag names (#2277)
* Regenerate sros sh lag keys in alphabetical order * Add error directive and patterns to Start state * Add basic matching for lag names * Add support for capturing sros lag name * Adjusted separator and condensed states - The output is simple enough to utilize just a Start state resulting in reduced duplication - Simplify a repeating pattern for the separators - and = - Simplify the regex for whitespace at the end of a data line
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4 files changed

Lines changed: 212 additions & 106 deletions

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‎ntc_templates/templates/alcatel_sros_show_lag.textfsm‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,17 @@ Value WEIGHTED (Yes|No)
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Value THRESHOLD (\d+)
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Value UP_COUNT (\d+)
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Value MC_ACT_STDBY (N/A|active|standby)
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Value LAG_NAME (lag-\S+)
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Start
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^----------- -> Lag
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Lag
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^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) -> Record
11+
^Lag\s+Data\s*$$
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^Lag-id\s+Adm\s+Opr\s+Weighted\s+Threshold\s+Up-Count\s+MC\s+Act/Stdby\s*$$
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^\s+name\s*$$
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^\d+\s+((up|down)\s+){2} -> Continue.Record
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^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}\s*$$
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^\s+${LAG_NAME}\s*$$
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^\s*$$
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^-----------
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^===========
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^===+
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^---+
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^Total
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^. -> Error

‎tests/alcatel_sros/show_lag/show_lag.yml‎

Lines changed: 131 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -1,219 +1,250 @@
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---
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parsed_sample:
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- lag_id: "1"
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adm: "up"
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- adm: "up"
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lag_id: "1"
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lag_name: ""
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mc_act_stdby: "N/A"
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opr: "up"
6-
weighted: "No"
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threshold: "0"
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up_count: "2"
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weighted: "No"
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- adm: "up"
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lag_id: "2"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "2"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "2"
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weighted: "No"
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- adm: "up"
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lag_id: "3"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "3"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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mc_act_stdby: "N/A"
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- lag_id: "4"
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adm: "down"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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- adm: "down"
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lag_id: "4"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "5"
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adm: "down"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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weighted: "No"
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- adm: "down"
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lag_id: "5"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "10"
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adm: "down"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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weighted: "No"
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- adm: "down"
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lag_id: "10"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "20"
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adm: "up"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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weighted: "No"
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- adm: "up"
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lag_id: "20"
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lag_name: ""
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mc_act_stdby: "standby"
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- lag_id: "70"
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adm: "down"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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weighted: "No"
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- adm: "down"
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lag_id: "70"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "80"
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adm: "up"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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weighted: "No"
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- adm: "up"
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lag_id: "80"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "90"
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adm: "down"
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opr: "down"
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weighted: "No"
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threshold: "0"
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up_count: "0"
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mc_act_stdby: "N/A"
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- lag_id: "100"
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adm: "up"
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opr: "up"
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weighted: "No"
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- adm: "down"
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lag_id: "90"
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lag_name: ""
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mc_act_stdby: "N/A"
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opr: "down"
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threshold: "0"
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up_count: "1"
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up_count: "0"
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weighted: "No"
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- adm: "up"
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lag_id: "100"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "101"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "101"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "102"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "102"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "103"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "103"
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lag_name: ""
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mc_act_stdby: "active"
101-
- lag_id: "104"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "104"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "105"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "105"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "106"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "106"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "107"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "107"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "108"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "108"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "109"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "109"
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lag_name: ""
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mc_act_stdby: "N/A"
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- lag_id: "110"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "110"
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lag_name: ""
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mc_act_stdby: "active"
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- lag_id: "111"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "111"
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lag_name: ""
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mc_act_stdby: "N/A"
157-
- lag_id: "112"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "112"
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lag_name: ""
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mc_act_stdby: "N/A"
164-
- lag_id: "114"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "114"
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lag_name: ""
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mc_act_stdby: "N/A"
171-
- lag_id: "115"
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adm: "up"
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opr: "up"
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weighted: "No"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "115"
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lag_name: ""
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mc_act_stdby: "N/A"
178-
- lag_id: "120"
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adm: "up"
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opr: "up"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "up"
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lag_id: "120"
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lag_name: ""
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mc_act_stdby: "N/A"
207+
opr: "up"
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threshold: "0"
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up_count: "1"
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weighted: "No"
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- adm: "down"
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lag_id: "124"
213+
lag_name: ""
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mc_act_stdby: "N/A"
185-
- lag_id: "124"
186-
adm: "down"
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opr: "down"
188-
weighted: "No"
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threshold: "0"
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up_count: "0"
218+
weighted: "No"
219+
- adm: "up"
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lag_id: "140"
221+
lag_name: ""
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mc_act_stdby: "N/A"
192-
- lag_id: "140"
193-
adm: "up"
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opr: "up"
195-
weighted: "No"
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threshold: "0"
197225
up_count: "1"
226+
weighted: "No"
227+
- adm: "down"
228+
lag_id: "150"
229+
lag_name: ""
198230
mc_act_stdby: "N/A"
199-
- lag_id: "150"
200-
adm: "down"
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opr: "down"
202-
weighted: "No"
203232
threshold: "0"
204233
up_count: "0"
205-
mc_act_stdby: "N/A"
206-
- lag_id: "153"
207-
adm: "up"
208-
opr: "up"
209234
weighted: "No"
235+
- adm: "up"
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lag_id: "153"
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lag_name: ""
238+
mc_act_stdby: "active"
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opr: "up"
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threshold: "0"
211241
up_count: "1"
212-
mc_act_stdby: "active"
213-
- lag_id: "180"
214-
adm: "down"
215-
opr: "down"
216242
weighted: "No"
243+
- adm: "down"
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lag_id: "180"
245+
lag_name: ""
246+
mc_act_stdby: "N/A"
247+
opr: "down"
217248
threshold: "0"
218249
up_count: "0"
219-
mc_act_stdby: "N/A"
250+
weighted: "No"

‎tests/alcatel_sros/show_lag/show_lag_name.raw‎

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@@ -0,0 +1,22 @@
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===============================================================================
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Lag Data
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===============================================================================
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Lag-id Adm Opr Weighted Threshold Up-Count MC Act/Stdby
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name
7+
-------------------------------------------------------------------------------
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1 up up No 0 1 N/A
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lag-1
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2 up up No 0 1 N/A
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lag-2
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19 up up No 0 2 N/A
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lag-19
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20 down down No 0 0 N/A
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lag-20
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50 down down No 0 0 N/A
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lag-myname
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101 up up No 0 1 N/A
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lag-101
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-------------------------------------------------------------------------------
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Total Lag-ids: 6 Single Chassis: 6 MC Act: 0 MC Stdby: 0
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===============================================================================

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