Merge branch 'master' into loom_s390_v1

Author: offamitkumar

make/devkit/Sysroot.gmk

@@ -88,8 +88,7 @@ SRCDIR := $(OUTPUT_ROOT)/src
 
 DOWNLOAD_RPMS_MARKER := $(BUILDDIR)/download-rpms.marker
 RPMS_UNPACKED_MARKER := $(BUILDDIR)/rpms_unpacked.marker
-UNPATCHED_SYSROOT_MARKER := $(BUILDDIR)/sysroot_unpatched.marker
-PATCHED_SYSROOT_MARKER := $(BUILDDIR)/sysroot_patched.marker
+SYSROOT_MARKER := $(BUILDDIR)/sysroot.marker
 
 ################################################################################
 # Download RPMs
@@ -101,10 +100,6 @@ else
 endif
 
 RPM_ARCHS := $(RPM_ARCH) noarch
-ifeq ($(ARCH), x86_64)
-  # Enable mixed mode.
-  RPM_ARCHS += i386 i686
-endif
 
 EMPTY :=
 SPACE := $(EMPTY) $(EMPTY)
@@ -166,43 +161,12 @@ $(RPMS_UNPACKED_MARKER): $(DOWNLOAD_RPMS_MARKER)
 
 ################################################################################
 
-$(UNPATCHED_SYSROOT_MARKER): $(RPMS_UNPACKED_MARKER)
+$(SYSROOT_MARKER): $(RPMS_UNPACKED_MARKER)
 	touch $@
 
-################################################################################
-# Patch sysroot
-
-# Note: MUST create a <sysroot>/usr/lib even if not really needed.
-# gcc will use a path relative to it to resolve lib64. (x86_64).
-# we're creating multi-lib compiler with 32bit libc as well, so we should
-# have it anyway, but just to make sure...
-# Patch GNU ld scripts to force linking against libraries in the sysroot
-# and not the ones installed on the build machine.
-
-LD_SCRIPT_PATCHES := \
-    -e 's|/usr/lib64/||g' \
-    -e 's|/usr/lib/||g' \
-    -e 's|/lib64/||g' \
-    -e 's|/lib/||g' \
-    #
-
-$(PATCHED_SYSROOT_MARKER): $(UNPATCHED_SYSROOT_MARKER)
-	@echo Patching GNU ld scripts
-	@( \
-	  for f in $$(find $(SYSROOT) -name "*.so" -type f 2>/dev/null); do \
-	    if grep -Iq 'GNU ld script' "$$f"; then \
-	      sed $(LD_SCRIPT_PATCHES) "$$f" > "$$f.tmp" && \
-	      mv "$$f.tmp" "$$f"; \
-	    fi; \
-	  done \
-	)
-	@mkdir -p $(SYSROOT)/usr/lib
-	@touch $@
-
 ################################################################################
 
 download-rpms: $(DOWNLOAD_RPMS_MARKER)
-unpatched-sysroot: $(UNPATCHED_SYSROOT_MARKER)
-sysroot: $(PATCHED_SYSROOT_MARKER)
+sysroot: $(SYSROOT_MARKER)
 
-.PHONY: download-rpms unpatched-sysroot sysroot
+.PHONY: download-rpms sysroot

make/devkit/Tools.gmk

@@ -103,16 +103,6 @@ ifneq ($(REQUIRED_MIN_MAKE_MAJOR_VERSION),)
 endif
 
 ################################################################################
-# Define common directories and files
-
-# Ensure we have 32-bit libs also for x64. We enable mixed-mode.
-ifeq (x86_64,$(ARCH))
-  LIBDIRS := lib64 lib
-  CFLAGS_lib := -m32
-else
-  LIBDIRS := lib
-endif
-
 # Define directories
 DOWNLOAD := $(OUTPUT_ROOT)/download
 SRCDIR := $(OUTPUT_ROOT)/src
@@ -200,23 +190,19 @@ TOOLS ?= $(call declare_tools,_FOR_TARGET,$(TARGET)-)
 
 ################################################################################
 
-# Create a TARGET bfd + libiberty only.
-# Configure one or two times depending on mulitlib arch.
-# If multilib, the second should be 32-bit, and we resolve
-# CFLAG_<name> to most likely -m32.
-define mk_bfd
-  $$(info Libs for $(1))
-  $$(BUILDDIR)/$$(BINUTILS_VER)-$(subst /,-,$(1))/Makefile: \
-      CFLAGS += $$(CFLAGS_$(1))
-  $$(BUILDDIR)/$$(BINUTILS_VER)-$(subst /,-,$(1))/Makefile: \
-      LIBDIRS = --libdir=$(TARGETDIR)/$(1)
-
-  BFDLIB += $$(TARGETDIR)/$$(BINUTILS_VER)-$(subst /,-,$(1)).done
-  BFDMAKES += $$(BUILDDIR)/$$(BINUTILS_VER)-$(subst /,-,$(1))/Makefile
-endef
+ifeq (x86_64,$(ARCH))
+  LIBDIR := lib64
+else
+  LIBDIR := lib
+endif
 
-# Create one set of bfds etc for each multilib arch
-$(foreach l,$(LIBDIRS),$(eval $(call mk_bfd,$(l))))
+$(BUILDDIR)/$(BINUTILS_VER)-$(LIBDIR)/Makefile:
+	CFLAGS += CFLAGS_$(LIBDIR)
+$(BUILDDIR)/$(BINUTILS_VER)-$(LIBDIR)/Makefile:
+	LIBDIR = --libdir=$(TARGETDIR)/$(LIBDIR)
+
+BFDLIB += $(TARGETDIR)/$(BINUTILS_VER)-$(LIBDIR).done
+BFDMAKES += $(BUILDDIR)/$(BINUTILS_VER)-$(LIBDIR)/Makefile
 
 # Only build these two libs.
 $(BFDLIB): MAKECMD = all-libiberty all-bfd
@@ -228,7 +214,7 @@ $(BFDMAKES): CONFIG = --target=$(TARGET) \
     --host=$(TARGET) --build=$(BUILD) \
     --prefix=$(TARGETDIR) \
     --with-sysroot=$(SYSROOT) \
-    $(LIBDIRS)
+    $(LIBDIR)
 
 $(BFDMAKES): TOOLS = $(call declare_tools,_FOR_TARGET,$(TARGET)-) $(call declare_tools,,$(TARGET)-)
 
@@ -243,11 +229,8 @@ $(GCC) \
     $(CCACHE): ENVS += $(TOOLS)
 
 # libdir to work around hateful bfd stuff installing into wrong dirs...
-# ensure we have 64 bit bfd support in the HOST library. I.e our
-# compiler on i686 will know 64 bit symbols, BUT later
-# we build just the libs again for TARGET, then with whatever the arch
-# wants.
-$(BUILDDIR)/$(BINUTILS_VER)/Makefile: CONFIG += --enable-64-bit-bfd --libdir=$(PREFIX)/$(word 1,$(LIBDIRS))
+# ensure we have 64 bit bfd support in the HOST library.
+$(BUILDDIR)/$(BINUTILS_VER)/Makefile: CONFIG += --enable-64-bit-bfd --libdir=$(PREFIX)/$(LIBDIR)
 
 ifeq ($(filter $(ARCH), s390x riscv64 ppc64le), )
   # gold compiles but cannot link properly on s390x @ gcc 13.2 and Fedore 41
@@ -256,10 +239,6 @@ ifeq ($(filter $(ARCH), s390x riscv64 ppc64le), )
   LINKER_CONFIG_ENABLE_GOLD := --enable-gold=default
 endif
 
-ifeq ($(filter riscv64 ppc64le s390x armhfp, $(ARCH)), )
-  ENABLE_MULTILIB := --enable-multilib
-endif
-
 # Makefile creation. Simply run configure in build dir.
 # Setting CFLAGS to -O2 generates a much faster ld.
 $(BFDMAKES) \
@@ -275,7 +254,6 @@ $(BUILDDIR)/$(BINUTILS_VER)/Makefile: $(BINUTILS_CFG)
 	      --with-sysroot=$(SYSROOT) \
 	      --disable-nls \
 	      --program-prefix=$(TARGET)- \
-	      $(ENABLE_MULTILIB) \
 	      --enable-threads \
 	      --enable-plugins \
 	) > $(@D)/log.config 2>&1
@@ -340,15 +318,12 @@ ifeq ($(ARCH), riscv64)
   $(BUILDDIR)/$(GCC_VER)/Makefile: CONFIG += --disable-libsanitizer
 endif
 
-ifneq ($(filter riscv64 ppc64le s390x armhfp, $(ARCH)), )
-  # We only support 64-bit on these platforms anyway
-  CONFIG += --disable-multilib
-endif
+# We don't need to support multilib
+CONFIG += --disable-multilib
 
 # Want:
 # c,c++
 # shared libs
-# multilib (-m32/-m64 on x64)
 # skip native language.
 # and link and assemble with the binutils we created
 # earlier, so --with-gnu*
@@ -438,14 +413,12 @@ ifeq ($(HOST),$(TARGET))
   # "Solve" this by create links from the target libdirs to where they are.
   $(LINK_LIBS_MARKER): $(GCC)
 	@echo -n 'Creating library symlinks...'
-	@for l in $(LIBDIRS); do \
-	  for f in `cd $(PREFIX)/$$l && ls`; do \
-	    if [ ! -e $(TARGETDIR)/$$l/$$f ]; then \
-	      mkdir -p $(TARGETDIR)/$$l && \
-	      cd $(TARGETDIR)/$$l/ && \
-	      ln -fs ../../$$l/$$f $$f; \
-	    fi \
-	  done \
+	@for f in `cd $(PREFIX)/$(LIBDIR) && ls`; do \
+	  if [ ! -e $(TARGETDIR)/$(LIBDIR)/$$f ]; then \
+	    mkdir -p $(TARGETDIR)/$(LIBDIR) && \
+	    cd $(TARGETDIR)/$(LIBDIR)/ && \
+	    ln -fs ../../$(LIBDIR)/$$f $$f; \
+	  fi \
 	done
 	@touch $@
 	@echo 'done'

src/hotspot/cpu/aarch64/aarch64.ad

@@ -8294,6 +8294,34 @@ instruct castII_checked(iRegI dst, rFlagsReg cr)
   ins_pipe(pipe_slow);
 %}
 
+// The unchecked and checked variants for CastII below both use iRegINoSp for src and dst
+// as some consumers of CastII node like ConvHF2F forbid the stack pointer as an input
+// (please see convHF2F_reg_reg rule which requires input to be in an iRegINoSp register).
+instruct castII_nosp(iRegINoSp dst)
+%{
+  predicate(VerifyConstraintCasts == 0);
+  match(Set dst (CastII dst));
+
+  size(0);
+  format %{ "# castII of $dst" %}
+  ins_encode(/* empty encoding */);
+  ins_cost(0);
+  ins_pipe(pipe_class_empty);
+%}
+
+instruct castII_checked_nosp(iRegINoSp dst, rFlagsReg cr)
+%{
+  predicate(VerifyConstraintCasts > 0);
+  match(Set dst (CastII dst));
+  effect(KILL cr);
+
+  format %{ "# castII_checked of $dst" %}
+  ins_encode %{
+    __ verify_int_in_range(_idx, bottom_type()->is_int(), $dst$$Register, rscratch1);
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 instruct castLL(iRegL dst)
 %{
   predicate(VerifyConstraintCasts == 0);

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -241,9 +241,9 @@ source %{
           return false;
         }
         break;
-      // At the time of writing this, the Vector API has no half-float (FP16) species.
-      // Consequently, AddReductionVHF and MulReductionVHF are only produced by the
-      // auto-vectorizer, which requires strictly ordered semantics for FP reductions.
+      // AddReductionVHF and MulReductionVHF are currently only produced by the
+      // auto-vectorizer (the Vector API does not yet intrinsify Float16 reductions),
+      // which requires strictly ordered semantics for FP reductions.
       //
       // There is no direct Neon instruction that performs strictly ordered floating
       // point add reduction. Hence, on Neon only machines, the add reduction operation
@@ -354,9 +354,9 @@ source %{
         opcode = Op_StoreVectorScatterMasked;
         break;
       // Currently, the masked versions of the following 8 Float16 operations are disabled.
-      // When the support for Float16 vector classes is added in VectorAPI and the masked
-      // Float16 IR can be generated, these masked operations will be enabled and relevant
-      // backend support added.
+      // The Vector API does not yet emit predicated Float16 IR. When such masked IR can be
+      // generated, these masked operations will be enabled and the relevant backend support
+      // added.
       case Op_AddVHF:
       case Op_SubVHF:
       case Op_MulVHF:

src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp

@@ -976,12 +976,9 @@ void ShenandoahBarrierStubC2::lrb(MacroAssembler& masm) {
     if (c_rarg0 == _obj) {
       __ lea(c_rarg1, _addr);
     } else if (c_rarg1 == _obj) {
-      // Set up arguments in reverse, and then flip them
-      __ lea(c_rarg0, _addr);
-      // flip them
-      __ mov(_tmp1, c_rarg0);
-      __ mov(c_rarg0, c_rarg1);
-      __ mov(c_rarg1, _tmp1);
+      __ mov(_tmp1, c_rarg1);
+      __ lea(c_rarg1, _addr);
+      __ mov(c_rarg0, _tmp1);
     } else {
       assert_different_registers(c_rarg1, _obj);
       __ lea(c_rarg1, _addr);

src/hotspot/cpu/arm/frame_arm.hpp

@@ -61,6 +61,7 @@
     // between a callee frame and its stack arguments, where it is part
     // of the caller/callee overlap
     metadata_words_at_top                            = 0,
+    // in bytes
     frame_alignment                                  = 16,
     // size, in words, of maximum shift in frame position due to alignment
     align_wiggle                                     =  1

src/hotspot/cpu/ppc/frame_ppc.hpp

@@ -402,8 +402,7 @@
     // between a callee frame and its stack arguments, where it is part
     // of the caller/callee overlap
     metadata_words_at_top                  = sizeof(java_abi) >> LogBytesPerWord,
-    // size, in words, of frame metadata at the frame top that needs
-    // to be reserved for callee functions in the runtime
+    // in bytes
     frame_alignment                        = 16,
     frame_alignment_in_words               = frame_alignment >> LogBytesPerWord,
     // size, in words, of maximum shift in frame position due to alignment

src/hotspot/cpu/ppc/gc/shenandoah/shenandoahBarrierSetAssembler_ppc.cpp

@@ -1210,12 +1210,9 @@ void ShenandoahBarrierStubC2::lrb(MacroAssembler& masm) {
     if (c_rarg0 == _obj) {
       __ addi(c_rarg1, _addr.base(), _addr.disp());
     } else if (c_rarg1 == _obj) {
-      // Set up arguments in reverse, and then flip them
-      __ addi(c_rarg0, _addr.base(), _addr.disp());
-      // flip them
-      __ mr(_tmp1, c_rarg0);
-      __ mr(c_rarg0, c_rarg1);
-      __ mr(c_rarg1, _tmp1);
+      __ mr(_tmp1, c_rarg1);
+      __ addi(c_rarg1, _addr.base(), _addr.disp());
+      __ mr(c_rarg0, _tmp1);
     } else {
       assert_different_registers(c_rarg1, _obj);
       __ addi(c_rarg1, _addr.base(), _addr.disp());

src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp

@@ -912,12 +912,9 @@ void ShenandoahBarrierStubC2::lrb(MacroAssembler& masm) {
     if (c_rarg0 == _obj) {
       __ la(c_rarg1, _addr);
     } else if (c_rarg1 == _obj) {
-      // Set up arguments in reverse, and then flip them
-      __ la(c_rarg0, _addr);
-      // flip them
-      __ mv(_tmp1, c_rarg0);
-      __ mv(c_rarg0, c_rarg1);
-      __ mv(c_rarg1, _tmp1);
+      __ mv(_tmp1, c_rarg1);
+      __ la(c_rarg1, _addr);
+      __ mv(c_rarg0, _tmp1);
     } else {
       assert_different_registers(c_rarg1, _obj);
       __ la(c_rarg1, _addr);

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -120,10 +120,10 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(bool, UseZvbb, false, EXPERIMENTAL, "Use Zvbb instructions")           \
   product(bool, UseZvbc, false, EXPERIMENTAL, "Use Zvbc instructions")           \
   product(bool, UseZvfh, false, DIAGNOSTIC, "Use Zvfh instructions")             \
-  product(bool, UseZvkn, false, EXPERIMENTAL,                                    \
+  product(bool, UseZvkg, false, DIAGNOSTIC, "Use Zvkg instructions")             \
+  product(bool, UseZvkn, false, DIAGNOSTIC,                                      \
           "Use Zvkn group extension, Zvkned, Zvknhb, Zvkb, Zvkt")                \
   product(bool, UseCtxFencei, false, EXPERIMENTAL,                               \
-          "Use PR_RISCV_CTX_SW_FENCEI_ON to avoid explicit icache flush")        \
-  product(bool, UseZvkg, false, EXPERIMENTAL, "Use Zvkg instructions")
+          "Use PR_RISCV_CTX_SW_FENCEI_ON to avoid explicit icache flush")
 
 #endif // CPU_RISCV_GLOBALS_RISCV_HPP