synth: blackbox SYNTH_BLACKBOXES modules before hierarchy check

Adds a checkpoint-based code path for SYNTH_BLACKBOXES to synth.tcl,
distinct from the existing source-based path in synth_preamble.tcl
in two intentional ways: it runs before `hierarchy -check -top`
(the design is already elaborated when read from RTLIL, so blackbox
operates on resolved modules), and it wraps `blackbox` in `catch`
(unknown names are silently skipped because the same SYNTH_BLACKBOXES
list is shared across partitions).

The synth_preamble.tcl path keeps its existing strict behaviour:
`hierarchy -check -top` first to elaborate the deferred verilog
top, and `blackbox` errors loudly so a typo in a single-design
SYNTH_BLACKBOXES list surfaces immediately.

Why this is needed: parallel partition synthesis with slang.

When `--keep-hierarchy` is used (required for partition flows that
preserve internal hierarchy), the slang frontend mangles module
names by their elaboration path so different parameterizations get
distinct names — `Foo` instantiated at `top.unit.foo` becomes
`Foo$top.unit.foo` in the elaborated RTLIL.  The parent design
references those mangled names.

A "per-partition canonicalize from RTL" approach therefore can't
just elaborate `Foo` as a fresh top — that would emit a module
named `Foo`, but the parent design instantiates `Foo$top.unit.foo`,
and the link fails.  The driver has to canonicalize the full design
once (so all parameterized instances get their elaborated names),
and each partition then loads that shared checkpoint and blackboxes
the modules outside its scope.

That's the orchestrator pattern: every partition reads the same
canonical RTLIL checkpoint and blackboxes the modules that belong
to other partitions, so it only synthesises its own subhierarchy.

SYNTH_BLACKBOXES is already documented in variables.yaml.

No behaviour change when the env var is unset.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

Author: oharboe

flow/scripts/synth.tcl

@@ -38,6 +38,32 @@ if { [env_var_exists_and_non_empty SYNTH_CHECKPOINT] } {
   read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil
 }
 
+# When this synthesis run is one partition of a parallel split (driven by
+# an external orchestrator), `SYNTH_BLACKBOXES` lists modules outside this
+# partition.  Blackboxing them before the hierarchy check lets each
+# partition load the same canonical RTLIL checkpoint while only synthesising
+# its own subhierarchy.  Names not present in the loaded design are skipped
+# silently so the same list can be passed to every partition.
+#
+# This deliberately differs from the SYNTH_BLACKBOXES handling in
+# synth_preamble.tcl's `read_design_sources`, and the difference is correct
+# in both places — do not "harmonise" the two:
+#   * Order: here the design is already elaborated (read from RTLIL), so
+#     `blackbox` operates on resolved modules and must run before the
+#     hierarchy check.  In synth_preamble.tcl the verilog frontend uses
+#     `read_verilog -defer`, so `hierarchy -check -top` must run first to
+#     elaborate from the top before `blackbox` sees a populated module table.
+#   * Catch: here a missing name is expected because the same list is
+#     reused across partitions, and only this partition's portion exists in
+#     the checkpoint.  In synth_preamble.tcl a single design is being
+#     synthesised, so an unknown name is almost certainly a user typo and
+#     should fail loudly — `blackbox $m` without `catch` is intentional.
+if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } {
+  foreach m $::env(SYNTH_BLACKBOXES) {
+    catch { blackbox $m }
+  }
+}
+
 hierarchy -check -top $::env(DESIGN_NAME)
 
 if { $::env(SYNTH_GUT) } {