synth: blackbox SYNTH_BLACKBOXES modules before hierarchy check

Adds a checkpoint-based code path for SYNTH_BLACKBOXES to synth.tcl,
and adds `catch` to the existing source-based path in
synth_preamble.tcl so unknown names are skipped silently in both
flows.  The two paths legitimately keep different orderings:

- synth.tcl reads a pre-elaborated RTLIL checkpoint, so blackbox runs
  before `hierarchy -check -top` (operating on already-resolved modules).
- synth_preamble.tcl reads source verilog with `read_verilog -defer`,
  so `hierarchy -check -top` must run first to elaborate from the top
  before blackbox can operate on the resolved module table.

Why this is needed: parallel partition synthesis with slang.

When `--keep-hierarchy` is used (required for partition flows that
preserve internal hierarchy), the slang frontend mangles module
names by their elaboration path so different parameterizations get
distinct names — `Foo` instantiated at `top.unit.foo` becomes
`Foo$top.unit.foo` in the elaborated RTLIL.  The parent design
references those mangled names.

A "per-partition canonicalize from RTL" approach therefore can't
just elaborate `Foo` as a fresh top — that would emit a module
named `Foo`, but the parent design instantiates `Foo$top.unit.foo`,
and the link fails.  The driver has to canonicalize the full design
once (so all parameterized instances get their elaborated names),
and each partition then loads that shared checkpoint and blackboxes
the modules outside its scope.

That's the orchestrator pattern: every partition reads the same
canonical RTLIL checkpoint and blackboxes the modules that belong
to other partitions, so it only synthesises its own subhierarchy.
The same SYNTH_BLACKBOXES list is reused across partitions, so
unknown names are skipped silently with `catch { blackbox $m }`
instead of erroring.

SYNTH_BLACKBOXES is already documented in variables.yaml.

No behaviour change when the env var is unset.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

Author: oharboe

flow/scripts/synth.tcl

@@ -38,6 +38,18 @@ if { [env_var_exists_and_non_empty SYNTH_CHECKPOINT] } {
   read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil
 }
 
+# When this synthesis run is one partition of a parallel split (driven by
+# an external orchestrator), `SYNTH_BLACKBOXES` lists modules outside this
+# partition.  Blackboxing them before the hierarchy check lets each
+# partition load the same canonical RTLIL checkpoint while only synthesising
+# its own subhierarchy.  Names not present in the loaded design are skipped
+# silently so the same list can be passed to every partition.
+if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } {
+  foreach m $::env(SYNTH_BLACKBOXES) {
+    catch { blackbox $m }
+  }
+}
+
 hierarchy -check -top $::env(DESIGN_NAME)
 
 if { $::env(SYNTH_GUT) } {

flow/scripts/synth_preamble.tcl

@@ -129,7 +129,7 @@ proc read_design_sources { } {
     if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } {
       hierarchy -check -top $::env(DESIGN_NAME)
       foreach m $::env(SYNTH_BLACKBOXES) {
-        blackbox $m
+        catch { blackbox $m }
       }
     }
   } else {