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malibertymaliberty
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Merge pull request The-OpenROAD-Project#4294 from The-OpenROAD-Project-staging/secure-fix-cts-propagated-clock
flow: Use Virtual Clocks for IO Delays
2 parents dcf6897 + a7d79fb commit a89f995

124 files changed

Lines changed: 17051 additions & 16629 deletions

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‎flow/designs/asap7/aes-block/rules-base.json‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__canonical_netlist__hash": {
3-
"value": "83fdb355d67936eac58202298e680864403e2e7c",
3+
"value": "3fc8a6d24fdb16116484d2eed15ff2dbe4531126",
44
"compare": "==",
55
"level": "warning"
66
},
@@ -10,39 +10,39 @@
1010
"level": "warning"
1111
},
1212
"synth__design__instance__area__stdcell": {
13-
"value": 1930.0,
13+
"value": 631.0,
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
1717
"value": 1,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {
21-
"value": 6699,
21+
"value": 6705,
2222
"compare": "<="
2323
},
2424
"placeopt__design__instance__count__stdcell": {
25-
"value": 9621,
25+
"value": 10214,
2626
"compare": "<="
2727
},
2828
"detailedplace__design__violations": {
2929
"value": 0,
3030
"compare": "=="
3131
},
3232
"cts__design__instance__count__setup_buffer": {
33-
"value": 837,
33+
"value": 888,
3434
"compare": "<="
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},
3636
"cts__design__instance__count__hold_buffer": {
37-
"value": 837,
37+
"value": 888,
3838
"compare": "<="
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},
4040
"cts__timing__setup__ws": {
41-
"value": -89.2,
41+
"value": -84.1,
4242
"compare": ">="
4343
},
4444
"cts__timing__setup__tns": {
45-
"value": -3220.0,
45+
"value": -4320.0,
4646
"compare": ">="
4747
},
4848
"cts__timing__hold__ws": {
@@ -58,11 +58,11 @@
5858
"compare": "<="
5959
},
6060
"globalroute__timing__setup__ws": {
61-
"value": -22.5,
61+
"value": -31.1,
6262
"compare": ">="
6363
},
6464
"globalroute__timing__setup__tns": {
65-
"value": -90.0,
65+
"value": -174.0,
6666
"compare": ">="
6767
},
6868
"globalroute__timing__hold__ws": {
@@ -74,7 +74,7 @@
7474
"compare": ">="
7575
},
7676
"detailedroute__route__wirelength": {
77-
"value": 49870,
77+
"value": 50261,
7878
"compare": "<="
7979
},
8080
"detailedroute__route__drc_errors": {
@@ -90,11 +90,11 @@
9090
"compare": "<="
9191
},
9292
"finish__timing__setup__ws": {
93-
"value": -31.5,
93+
"value": -56.6,
9494
"compare": ">="
9595
},
9696
"finish__timing__setup__tns": {
97-
"value": -123.0,
97+
"value": -1520.0,
9898
"compare": ">="
9999
},
100100
"finish__timing__hold__ws": {
@@ -106,7 +106,7 @@
106106
"compare": ">="
107107
},
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"finish__design__instance__area": {
109-
"value": 6742,
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"value": 6750,
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"compare": "<="
111111
}
112112
}

‎flow/designs/asap7/aes-mbff/rules-base.json‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14,35 +14,35 @@
1414
"compare": "<="
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},
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"constraints__clocks__count": {
17-
"value": 1,
17+
"value": 2,
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"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {
21-
"value": 1898,
21+
"value": 1897,
2222
"compare": "<="
2323
},
2424
"placeopt__design__instance__count__stdcell": {
25-
"value": 18142,
25+
"value": 18134,
2626
"compare": "<="
2727
},
2828
"detailedplace__design__violations": {
2929
"value": 0,
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"compare": "=="
3131
},
3232
"cts__design__instance__count__setup_buffer": {
33-
"value": 1578,
33+
"value": 1577,
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"compare": "<="
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},
3636
"cts__design__instance__count__hold_buffer": {
37-
"value": 1578,
37+
"value": 1577,
3838
"compare": "<="
3939
},
4040
"cts__timing__setup__ws": {
41-
"value": -21.6,
41+
"value": -20.8,
4242
"compare": ">="
4343
},
4444
"cts__timing__setup__tns": {
45-
"value": -78.6,
45+
"value": -77.8,
4646
"compare": ">="
4747
},
4848
"cts__timing__hold__ws": {
@@ -58,11 +58,11 @@
5858
"compare": "<="
5959
},
6060
"globalroute__timing__setup__ws": {
61-
"value": -19.5,
61+
"value": -19.0,
6262
"compare": ">="
6363
},
6464
"globalroute__timing__setup__tns": {
65-
"value": -76.5,
65+
"value": -76.0,
6666
"compare": ">="
6767
},
6868
"globalroute__timing__hold__ws": {
@@ -74,7 +74,7 @@
7474
"compare": ">="
7575
},
7676
"detailedroute__route__wirelength": {
77-
"value": 68982,
77+
"value": 69120,
7878
"compare": "<="
7979
},
8080
"detailedroute__route__drc_errors": {
@@ -90,11 +90,11 @@
9090
"compare": "<="
9191
},
9292
"finish__timing__setup__ws": {
93-
"value": -19.0,
93+
"value": -20.8,
9494
"compare": ">="
9595
},
9696
"finish__timing__setup__tns": {
97-
"value": -76.0,
97+
"value": -77.8,
9898
"compare": ">="
9999
},
100100
"finish__timing__hold__ws": {
@@ -106,7 +106,7 @@
106106
"compare": ">="
107107
},
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"finish__design__instance__area": {
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"value": 1947,
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"value": 1942,
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"compare": "<="
111111
}
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}

‎flow/designs/asap7/aes/constraint.sdc‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,12 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
create_clock -name $clk_name -period $clk_period $clk_port
9+
set clk_io_name vclk_$clk_name
10+
create_clock -name $clk_io_name -period $clk_period
11+
set_clock_latency 77.930 [get_clocks $clk_name]
12+
set_clock_latency 77.930 [get_clocks $clk_io_name]
913

1014
set non_clock_inputs [all_inputs -no_clocks]
1115

12-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
16+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
17+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]

‎flow/designs/asap7/aes/rules-base.json‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -10,39 +10,39 @@
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"level": "warning"
1111
},
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"synth__design__instance__area__stdcell": {
13-
"value": 1780.0,
13+
"value": 1610.0,
1414
"compare": "<="
1515
},
1616
"constraints__clocks__count": {
17-
"value": 1,
17+
"value": 2,
1818
"compare": "=="
1919
},
2020
"placeopt__design__instance__area": {
21-
"value": 1849,
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"value": 1614,
2222
"compare": "<="
2323
},
2424
"placeopt__design__instance__count__stdcell": {
25-
"value": 17477,
25+
"value": 14476,
2626
"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
3131
},
3232
"cts__design__instance__count__setup_buffer": {
33-
"value": 1520,
33+
"value": 1259,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
37-
"value": 1520,
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"value": 1259,
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"compare": "<="
3939
},
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"cts__timing__setup__ws": {
41-
"value": -19.0,
41+
"value": -28.9,
4242
"compare": ">="
4343
},
4444
"cts__timing__setup__tns": {
45-
"value": -76.0,
45+
"value": -119.0,
4646
"compare": ">="
4747
},
4848
"cts__timing__hold__ws": {
@@ -58,11 +58,11 @@
5858
"compare": "<="
5959
},
6060
"globalroute__timing__setup__ws": {
61-
"value": -19.5,
61+
"value": -28.0,
6262
"compare": ">="
6363
},
6464
"globalroute__timing__setup__tns": {
65-
"value": -169.0,
65+
"value": -164.0,
6666
"compare": ">="
6767
},
6868
"globalroute__timing__hold__ws": {
@@ -74,7 +74,7 @@
7474
"compare": ">="
7575
},
7676
"detailedroute__route__wirelength": {
77-
"value": 60637,
77+
"value": 57961,
7878
"compare": "<="
7979
},
8080
"detailedroute__route__drc_errors": {
@@ -90,11 +90,11 @@
9090
"compare": "<="
9191
},
9292
"finish__timing__setup__ws": {
93-
"value": -20.8,
93+
"value": -24.2,
9494
"compare": ">="
9595
},
9696
"finish__timing__setup__tns": {
97-
"value": -77.8,
97+
"value": -87.7,
9898
"compare": ">="
9999
},
100100
"finish__timing__hold__ws": {
@@ -106,7 +106,7 @@
106106
"compare": ">="
107107
},
108108
"finish__design__instance__area": {
109-
"value": 1884,
109+
"value": 1664,
110110
"compare": "<="
111111
}
112112
}

‎flow/designs/asap7/ethmac/constraint.sdc‎

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,29 +3,41 @@ set clk_period 1000
33
set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set top_io_clk_name vclk_$top_clk_name
7+
create_clock -name $top_io_clk_name -period $clk_period
8+
set_clock_latency 229.195 [get_clocks $top_clk_name]
9+
set_clock_latency 229.195 [get_clocks $top_io_clk_name]
610
set non_clock_inputs [all_inputs -no_clocks]
7-
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
8-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
11+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name $non_clock_inputs
12+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_io_clk_name [all_outputs]
913

1014
set tx_clk_name mtx_clk_pad_i
1115
set tx_clk_port [get_ports $tx_clk_name]
1216
set tx_clk_period 300
1317
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
18+
set tx_io_clk_name vclk_$tx_clk_name
19+
create_clock -name $tx_io_clk_name -period $tx_clk_period
20+
set_clock_latency 55.660 [get_clocks $tx_clk_name]
21+
set_clock_latency 55.660 [get_clocks $tx_io_clk_name]
1422
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $tx_clk_port]
15-
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name $mtx_non_clock_inputs
16-
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_clk_name [all_outputs]
23+
set_input_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name $mtx_non_clock_inputs
24+
set_output_delay [expr $tx_clk_period * $clk_io_pct] -clock $tx_io_clk_name [all_outputs]
1725

1826
set rx_clk_name mrx_clk_pad_i
1927
set rx_clk_port [get_ports $rx_clk_name]
2028
set rx_clk_period 300
2129
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
30+
set rx_io_clk_name vclk_$rx_clk_name
31+
create_clock -name $rx_io_clk_name -period $rx_clk_period
32+
set_clock_latency 76.515 [get_clocks $rx_clk_name]
33+
set_clock_latency 76.515 [get_clocks $rx_io_clk_name]
2234
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $rx_clk_port]
23-
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name $mrx_non_clock_inputs
24-
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_clk_name [all_outputs]
35+
set_input_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name $mrx_non_clock_inputs
36+
set_output_delay [expr $rx_clk_period * $clk_io_pct] -clock $rx_io_clk_name [all_outputs]
2537

2638
set_clock_groups -name core_clock -logically_exclusive \
27-
-group [get_clocks $top_clk_name] \
28-
-group [get_clocks $tx_clk_name] \
29-
-group [get_clocks $rx_clk_name]
39+
-group [concat [get_clocks $top_clk_name] [get_clocks $top_io_clk_name]] \
40+
-group [concat [get_clocks $tx_clk_name] [get_clocks $tx_io_clk_name]] \
41+
-group [concat [get_clocks $rx_clk_name] [get_clocks $rx_io_clk_name]]
3042

3143
set_max_fanout 10 [current_design]

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