Update yosys submodule#56
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Adds a --jobName argument to flow/util/uploadMetadata.py so the QoR metadata published to Pub/Sub can carry the canonical Jenkins pipeline name. When supplied (and non-blank after stripping whitespace), the message is emitted as schema v3 (the v2 structure plus a top-level job_name); otherwise the script behaves as before and emits v2. This lets the palantir backend resolve the pipeline directly from job_name instead of classifying the raw BUILD_TAG with a hardcoded pattern table, so new pipelines appear on the dashboard without a backend code change. The >8 MB per-design fallback path is unchanged - it still emits v1 messages, which the backend continues to resolve via BUILD_TAG. Signed-off-by: Miguel Pedro <miguel.pedro@precisioninno.com>
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Create virtual IO reference clocks for SDC input and output delay constraints so post-CTS propagated real clocks do not become the external timing reference. Propagate only the real design clocks in post-CTS SDCs while preserving virtual clock latency for IO timing. Update the OpenROAD submodule pointer to include the CTS virtual clock latency fix used by these constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Rebase metric thresholds for designs affected by the updated OpenROAD build used in CI.\n\nAdjust timing and antenna limits to match the observed public and secure CI outputs while preserving existing metric coverage.\n\nExclude the local OpenROAD submodule checkout change from this commit. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Set real and virtual IO clock latency estimates from propagated CTS clock latency reported in CI artifacts. Use the representative average of source and target clock latency from 4_cts_final reports so IO virtual clocks track observed post-CTS insertion delay more closely. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Relax metric thresholds for designs affected by the updated IO clock latency estimates. Use the latest public and secure CI results to update timing and wirelength rules for failing designs. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Brings up the GT2N 2nm GAAFET PDK with buried-power-rail (BSPDN) and
runs gcd through it end-to-end with the OpenROAD changes on the
bspdn branch of tools/OpenROAD.
* flow/platforms/gt2n/ new platform:
config.mk top-level platform variables.
fastroute.tcl, pdn.tcl, setRC.tcl, tapcell.tcl, cells_clkgate.v
ORFS step config; PDN is BPR followpins
only (backside rails come from elsewhere).
lef/, lib/, gds/ copy of the GT2N tt w31 LVT collateral.
gt2.lyt, gt2.lyp KLayout tech + per-layer colors (rainbow
for front-side M0..M13 + RDL, warm/red
shades for backside BPR/BM*/BRDL).
gt2.layermap LEF layer -> GDS layer mapping.
LICENSE, README.md upstream attribution.
The local copy of gt2_6t_w31_lvt.lef carries a small authoring fix
on the gt2_6t_tap_w31_lvt cell: BPR shapes that were declared as
OBS are moved into a second PORT on each PG pin so the LEF
correctly encodes the M1<->BPR bridge. Suggested upstream as
azadnaeemi/GT2N#12.
* flow/designs/gt2n/gcd/ new design:
config.mk, constraint.sdc
* tools/OpenROAD bump to bspdn tip (0e7eabb59d) which adds
isBackside()/LEF58_BACKSIDE support and
filters backside layers out of DRT.
* tools/yosys pin to v0.64 release (6d2c445a) which
works around the Ubuntu 24.04 / glibc 2.39
yosys-abc pipe deadlock in newer SHAs.
* .gitignore whitelist flow/platforms/gt2n.
Verified: gt2n/gcd produces 6_final.{def,gds,odb,sdc,v}.
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
BPR followpins on their own do not stitch the per-row vdd/vss rails together, so the backside grid was a chain of disconnected horizontal strips. Add a two-layer perpendicular mesh (BM1 vertical, BM2 horizontal) plus BV0/BV1 connects, modeled on asap7's M5/M6 over M1/M2 followpin pattern. Top of the standard-cell grid is now BM2. Also adds resistance values for the backside cut layers (BV0..BV4) to setRC.tcl so PSM's analyze_power_grid does not error out with PSM-0021 when the PG network includes backside vias. Calls out that every RC value in this file is a placeholder, not silicon-calibrated. Verified end-to-end on gt2n/gcd: 873s wall time, 0 DRC violations, 0 ANT violations. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Upstream commit 42e1034 ("Update gt2_6t_w31_lvt.lef") moves the BPR
shapes on the tap cell from OBS to PORT (the issue #12 fix we
needed), but in the same commit it also renames the macro
`gt2_6t_tap_w31_lvt` into a split `gt2_6t_tapfspdn_w31_lvt` /
`gt2_6t_tapbspdn_w31_lvt` pair in the LEF and lib. The matching GDS
cells for the new names were not added upstream
(azadnaeemi/GT2N#16), so the post-rename PDK is internally
inconsistent: the LEF/lib advertise two new tap-cell names, but
neither exists in the GDS, only the original `gt2_6t_tap_w31_lvt`
does. KLayout GDS-merge at the end of the flow cannot resolve the
tap instances and the final GDS is incomplete.
Keep the BPR PORT geometry from the upstream commit (this is the
fix we wanted) but undo the rename here: collapse the LEF macros
and lib cells back into a single `gt2_6t_tap_w31_lvt`, point
TAP_CELL_NAME and DONT_USE_CELLS at it, and update the README to
explain the situation and link to the upstream issue tracking the
GDS gap. Revisit once upstream #16 is resolved.
Smoke: gt2n/gcd 2_3_floorplan_tapcell clean (110 endcaps + 28
tapcells inserted).
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
M5 was a conservative bring-up cap so routing did not have to deal with the full GT2N stack while we were stabilising the platform. The tech has frontside routing layers M0..M13 + RDL; M13 is the topmost regular routing layer (RDL is the redistribution / top-metal). Open up MAX_ROUTING_LAYER to M13 so larger designs can use the full BEOL. Verified end-to-end on gt2n/gcd: full flow through 6_final clean, final GDS produced, no DRC / antenna violations. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
The platform was bringing up a single (w31, lvt) corner. Upstream 308b221 ships ten W/Vt combinations at tt 0.7V/25C: w13 (13 nm nanosheet) and w31 (31 nm), each in hvt / svt / lvt / ulvt / elvt. All ten use the same gt2_6t site (0.042 x 0.144) and the same tech LEF, so any subset of (W, Vt) tuples can coexist in a single block and synthesis can size + W/Vt-trade across the full menu. Vendor the nine new (W, Vt) triplets directly from upstream 308b221 (LEF + lib + GDS, all with the tap-cell split intact), and parameterise the platform config on two ordered lists modelled on asap7's ASAP7_USE_VT pattern: GT2N_USE_W nanosheet-width families to load. Default: 'w31'. GT2N_USE_VT Vt flavors to load. Default: 'lvt hvt svt ulvt elvt'. The first word of each list is the primary value. The (primary W, primary Vt) tuple drives canonical single-cell references (tap, tiehi/tielo, buffer, ABC driver); the rest of the Cartesian product rides along as additional LEF / lib / GDS so Yosys + ABC see every loaded sizing option. Includes the upstream lib refresh (default_operating_conditions, voltage_map, pg_pin annotations on every cell). Smoke: gt2n/gcd full flow clean, EXIT=0. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
The platform ships both nanosheet widths (w13 = 13 nm sheet, w31 = 31 nm sheet) and they share the same gt2_6t site, so loading both into a single block costs nothing in placement and lets ABC pick across the full 2 W x 5 Vt = 10 (W, Vt) menu. Default GT2N_USE_W to "w31 w13" so every gt2n design sees the menu without having to override the list in each per-design config.mk. Single-width builds still work by setting GT2N_USE_W to "w31" or "w13" in the design config. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
The C values in setRC.tcl were placeholders ("the ICT shipped with the
PDK does not contain extracted C ... should be replaced with values
from a calibrated RCX/QRC model before treating any C-derived quantity
as physical"). The R values were derived from Fig 1(b) of the GT2N
paper and were already grounded, but the via R was a fake "scaled
roughly by cut size" stand-in.
The PDK's StarRC ITF file (GT2N/nxtgrd/GT2.itf) carries enough physical
data to derive both R and C analytically: per-layer RPSQ, dielectric
thickness and permittivity above and below each conductor, conductor
thickness, WMIN, SMIN, and per-VIA RPV. Use those to compute:
R/um = RPSQ / WMIN
C/um = (Ca + Cb) * fringe_factor + 2 * Cc (fF/um, then to pF/um)
Ca = eps0 * eps_above * W / d_above
Cb = eps0 * eps_below * W / d_below
Cc = eps0 * eps_side * T_wire / SMIN
fringe_factor = 1.5x coarse fringe-field correction
Via R = RPV (single via, from ITF VIA entries)
itf_to_rc.py drops next to the platform so the derivation is
reproducible; setRC.tcl is its output rendered into set_layer_rc
commands plus the existing set_wire_rc selections.
These numbers are still approximate -- the proper fix is real RCX
extraction (run a 3D solver, e.g. FasterCap, against OpenRCX's pattern
DEFs and feed the resulting SPEF to OpenRCX generate_rules.tcl). The
ITF/NXTGRD/QRC files in GT2N/ carry everything that pipeline needs.
The analytical table is the working stand-in until those rules exist.
Smoke (gt2n/gcd full flow): clean, EXIT=0. Achieved core_clock period
moves from 373.6 ps (placeholder C) to 344.6 ps (analytical C); slack
goes from 106.8 ps to 137.3 ps. Lower C reduces wire delay, so timing
reports tighter -- consistent with the analytical C being ~33-60%
below the placeholder, which itself had no physical grounding.
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Default tapcell.tcl was using `-distance 5` (5 um between taps along each row), which is loose enough that small designs end up with a single tap column. The gt2n tap cell does double duty: it is both the well/body-bias tap (the conventional purpose) and the per-row M1<->BPR or sole BPR riser for the BSPDN power network -- each tap is the only hard via from the cell row's BPR rail into the BSPDN power source. Tap density therefore directly sets per-row BPR resistance and the worst-case BSPDN IR drop, which is not true in flows where taps only exist for latchup avoidance. Drop `-distance` to 2 um. On gt2n/gcd (4-5 um core side, 55 rows): -distance 5 2 tapcells 28 114 (+4x) vdd worst 10.9 mV 8.49 mV (-22%) vdd avg 2.62 mV 2.59 mV vss worst 7.25 mV 7.35 mV (essentially same, already well distrib) vss avg 2.27 mV 2.27 mV (IR numbers from analyze_power_grid on 6_final.odb with leakage-only currents -- absolute drop is small at this design size, but the worst-case-vdd improvement is what we expect from more BPR risers.) Detail-route runtime goes up roughly 3x because of the denser obstacle field, but converges cleanly to 0 DRC + 0 antenna. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
Adds jpeg_encoder as a larger reference benchmark alongside gcd and aes -- representative of designs that meaningfully exercise the upper-stack routing layers and the multi-W / multi-Vt library menu. config.mk mirrors the asap7 / nangate45 jpeg configurations (ABC_AREA=1, TNS_END_PERCENT=100, conservative CORE_UTILIZATION). constraint.sdc uses a 1500 ps clock as a first-pass loose target; period_min lands around 950 ps so the design has substantial headroom to tighten once OpenRCX rules replace the analytical RC. Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
The platform exposes metal up to M13, but the reference designs route well below that (gcd uses up to M5, jpeg M9, aes M10; layers above carry no wire). Pinning MAX_ROUTING_LAYER at the platform M13 top forced detailed routing to build its grid graph, via stack, and DRC checks across the full layer range for every design, inflating runtime and memory. Move MAX_ROUTING_LAYER out of the platform config (leaving a comment) and set it per design at the highest layer each actually uses. gcd@M5 was verified to route DRC-clean; aes/jpeg caps only drop layers that carry zero wire. Signed-off-by: mrg <mrg@ucsc.edu>
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
Note where GT2.itf comes from (the StarRC interconnect tech file shipped with the GT2N PDK, not in this repo) and the matching NXTGRD/QRC files, mirroring the existing setRC.tcl header, and point readers to the platform README for additional GT2N information. itf_to_rc.py also flags that __main__ hardcodes a local path to the ITF that must be adjusted to a local PDK copy. Comments only. Signed-off-by: mrg <mrg@ucsc.edu>
…t-staging/update-or update OpenROAD
Add rules-base.json baselines for the gcd, aes, and jpeg gt2n designs, generated via 'make metadata' + 'make update_ok' from a clean run at each design's committed MAX_ROUTING_LAYER (M5/M10/M9) on the pinned OpenROAD. All three route DRC-clean; metadata-check passes with 0 failures/warnings. This gives the gt2n designs CI metadata baselines (previously absent). Signed-off-by: mrg <mrg@ucsc.edu>
gt2n: add 2nm BSPDN platform with gcd and aes designs
The phony check-klayout target was a normal prerequisite of $(GDS_MERGED_FILE), which forced the KLayout def2stream merge to re-run on every `make finish`/`make metadata` invocation regardless of whether the GDS inputs had changed. Moving it behind `|` keeps the KLayout availability check when the GDS needs building, without marking the GDS perpetually out-of-date. Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
…t-staging/fix-gds-rebuild-check-klayout Make check-klayout an order-only prereq of merged GDS
Update the OpenROAD submodule to the private secure-fix-cts-propagated-clock commit that preserves virtual clock latency during CTS. This lets the SDC virtual IO clock latency changes affect post-CTS timing and downstream QoR in CI. Only the OpenROAD submodule pointer is changed. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
…agated-clock # Conflicts: # tools/OpenROAD Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update metadata golden files for the public PR-4294 merge run. Use the PR-4294-merge #10 report metrics for designs that failed the public inline metric comparison so the expected metric baseline matches the virtual IO clock constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Revert the deprecated metadata-base-ok.json updates from the previous metric rebase. Update rules-base.json for the public PR-4294 merge run using the reported metrics so the public metric checks match the virtual IO clock constraints. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update the gf12 ariane rules baseline from secure CI build 16. Relax the CTS setup TNS rule to match the virtual IO clock timing result while keeping deprecated metadata-base-ok.json files untouched. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Add an empty commit to retrigger the public PR merge CI after the rules rebase. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
…t-staging/ci-jobname-support ci: support for jobName flag and v3 messages
…t-staging/secure-fix-cts-propagated-clock flow: Use Virtual Clocks for IO Delays
Allows you to see the data in the inspector. Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
…t-staging/view_cells-with-liberty Load the Liberty in view_cells.tcl
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
…t-staging/update-or update OR for pdn changes
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Add flow/util/plot_wns.py, a local (no-bazel) script that reads the committed rules-base.json baselines and regenerates, per PDK, a worst-setup-slack bar chart (wns.png) and a "## WNS" README section between generated markers. It covers all 9 PDKs that ship timing baselines (76 designs); the bar is finish-stage WNS, with cts and globalroute drawn as markers so stage-to-stage movement is visible. No OpenROAD/ORFS run is required -- the data already lives in the tree, so the plots are deterministic and the committed PNGs + tables render on GitHub with nothing to run. asap7/README.md additionally carries a hand-written findings section discussing the results. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Extend plot_wns.py to quantify how well the cts and globalroute worst-slack estimates predict the final WNS. Each design's per-stage error (stage - finish) is normalized by its clock period, parsed from the .sdc, so PDKs with different timing units are comparable. Adds flow/designs/wns_accuracy.png (per-PDK strip plot of normalized estimate error, + optimistic / - pessimistic) and a new flow/designs/README.md with a "## WNS estimate accuracy across PDKs" section: a per-PDK MAE/bias table plus hand-written findings. Covers the 67 designs across 8 PDKs that expose cts/globalroute slack and a parsable clock period; the rest are noted as omitted. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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