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oliver-joosdpgeorge
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stm32/boards/NUCLEO_H7x3: Fix st-flash and add openocd configuration.
To connect STM32H7 that is in SLEEPD1 state (e.g. during REPL) debuggers like st-flash or openocd must assert SRST. Signed-off-by: Oliver Joos <oliver.joos@hispeed.ch>
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ports/stm32/boards/NUCLEO_H723ZG/mpconfigboard.mk

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@@ -24,3 +24,7 @@ MICROPY_VFS_LFS2 = 1
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MICROPY_HW_ENABLE_ISR_UART_FLASH_FUNCS_IN_RAM = 1
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FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
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# Flash tool configuration
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STFLASH = st-flash --connect-under-reset
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OPENOCD_CONFIG = boards/openocd_stm32h7_dual_bank.cfg

ports/stm32/boards/NUCLEO_H743ZI/mpconfigboard.mk

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@@ -24,3 +24,7 @@ MICROPY_VFS_LFS2 = 1
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MICROPY_HW_ENABLE_ISR_UART_FLASH_FUNCS_IN_RAM = 1
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FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
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# Flash tool configuration
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STFLASH = st-flash --connect-under-reset
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OPENOCD_CONFIG = boards/openocd_stm32h7_dual_bank.cfg
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# This script configures OpenOCD for use with an ST-Link V3 programmer/debugger
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# and an STM32H7 target microcontroller with 2MB RAM (dual bank).
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#
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# To flash your firmware:
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#
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# $ openocd -f boards/openocd_stm32h7_dual_bank.cfg \
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# -c "stm_flash build-BOARD/firmware.bin 0x08000000
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#
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# For a gdb server on port 3333:
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#
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# $ openocd -f boards/openocd_stm32h7_dual_bank.cfg
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source [find interface/stlink-dap.cfg]
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transport select dapdirect_swd
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source [find target/stm32h7x_dual_bank.cfg]
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reset_config srst_only connect_assert_srst
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init
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proc stm_flash { BIN0 ADDR0 {BIN1 ""} {ADDR1 ""} } {
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reset halt
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sleep 100
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wait_halt 2
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flash write_image erase $BIN0 $ADDR0
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sleep 100
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verify_image $BIN0 $ADDR0
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sleep 100
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if {$BIN1 ne ""} {
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flash write_image erase $BIN1 $ADDR1
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sleep 100
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verify_image $BIN1 $ADDR1
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sleep 100
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}
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reset run
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shutdown
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}
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proc stm_erase {} {
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reset halt
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sleep 100
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stm32h7x mass_erase 0
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sleep 100
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stm32h7x mass_erase 1
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sleep 100
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shutdown
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}

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