py/emitinlinextensa: Add inline assembler support for windowed cores.

This commit introduces support for writing inline assembler code
snippets when targeting Xtensa cores that use register windows (eg.
the whole ESP32 family).

Opcodes support is still limited to what the ESP8266 supports (as in,
LX3 cores opcodes), however each LX core version is guaranteed to
support all previous versions' opcodes as well.  The ESP32 does not have
the inline assembler enabled by default, following the existing
expectations when it comes to firmware footprint.

Since now emitted functions may have one of two possible exit sequences,
the L32I test had to be fixed.  It would return the word containing the
L32I opcode itself, but the upper 8 bits of the word came from the
following opcode - which can change depending on the exit code sequence.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

Author: agatti

py/asmxtensa.c

@@ -115,10 +115,12 @@ void asm_xtensa_exit(asm_xtensa_t *as) {
 }
 
 void asm_xtensa_entry_win(asm_xtensa_t *as, int num_locals) {
-    // jump over the constants
-    asm_xtensa_op_j(as, as->num_const * WORD_SIZE + 4 - 4);
-    mp_asm_base_get_cur_to_write_bytes(&as->base, 1); // padding/alignment byte
-    as->const_table = (uint32_t *)mp_asm_base_get_cur_to_write_bytes(&as->base, as->num_const * 4);
+    if (as->num_const > 0) {
+        // jump over the constants
+        asm_xtensa_op_j(as, as->num_const * WORD_SIZE + 4 - 4);
+        mp_asm_base_get_cur_to_write_bytes(&as->base, 1); // padding/alignment byte
+        as->const_table = (uint32_t *)mp_asm_base_get_cur_to_write_bytes(&as->base, as->num_const * 4);
+    }
 
     as->stack_adjust = 32 + ((((ASM_XTENSA_NUM_REGS_SAVED_WIN + num_locals) * WORD_SIZE) + 15) & ~15);
     asm_xtensa_op_entry(as, ASM_XTENSA_REG_A1, as->stack_adjust);

py/compile.c

@@ -147,7 +147,7 @@ static const emit_inline_asm_method_table_t *emit_asm_table[] = {
     &emit_inline_thumb_method_table,
     &emit_inline_thumb_method_table,
     &emit_inline_xtensa_method_table,
-    NULL,
+    &emit_inline_xtensa_method_table,
     &emit_inline_rv32_method_table,
 };
 
@@ -3551,7 +3551,7 @@ void mp_compile_to_raw_code(mp_parse_tree_t *parse_tree, qstr source_file, bool
             // TODO this can be improved by calculating it during SCOPE pass
             // but that requires some other structural changes to the asm emitters
             #if MICROPY_DYNAMIC_COMPILER
-            if (mp_dynamic_compiler.native_arch == MP_NATIVE_ARCH_XTENSA)
+            if (mp_dynamic_compiler.native_arch == MP_NATIVE_ARCH_XTENSA || mp_dynamic_compiler.native_arch == MP_NATIVE_ARCH_XTENSAWIN)
             #endif
             {
                 compile_scope_inline_asm(comp, s, MP_PASS_CODE_SIZE);

py/emitinlinextensa.c

@@ -35,6 +35,18 @@
 
 #if MICROPY_EMIT_INLINE_XTENSA
 
+#include "py/persistentcode.h"
+
+static inline bool emit_windowed_code() {
+    #if MICROPY_DYNAMIC_COMPILER
+    return mp_dynamic_compiler.native_arch == MP_NATIVE_ARCH_XTENSAWIN;
+    #elif MICROPY_EMIT_XTENSAWIN
+    return true;
+    #else
+    return false;
+    #endif
+}
+
 struct _emit_inline_asm_t {
     asm_xtensa_t as;
     uint16_t pass;
@@ -73,11 +85,19 @@ static void emit_inline_xtensa_start_pass(emit_inline_asm_t *emit, pass_kind_t p
         memset(emit->label_lookup, 0, emit->max_num_labels * sizeof(qstr));
     }
     mp_asm_base_start_pass(&emit->as.base, pass == MP_PASS_EMIT ? MP_ASM_PASS_EMIT : MP_ASM_PASS_COMPUTE);
-    asm_xtensa_entry(&emit->as, 0);
+    if (emit_windowed_code()) {
+        asm_xtensa_entry_win(&emit->as, 0);
+    } else {
+        asm_xtensa_entry(&emit->as, 0);
+    }
 }
 
 static void emit_inline_xtensa_end_pass(emit_inline_asm_t *emit, mp_uint_t type_sig) {
-    asm_xtensa_exit(&emit->as);
+    if (emit_windowed_code()) {
+        asm_xtensa_exit_win(&emit->as);
+    } else {
+        asm_xtensa_exit(&emit->as);
+    }
     asm_xtensa_end_pass(&emit->as);
 }
 

tests/inlineasm/xtensa/asmloadstore.py

@@ -1,8 +1,9 @@
 import array
 
-# On the 8266 the generated code gets put into the IRAM segment, which is only
-# word-addressable.  Therefore, to test byte and halfword load/store opcodes
-# some memory must be reserved in the DRAM segment.
+# On the ESP8266 the generated code gets put into the IRAM segment, which is
+# only word-addressable.  Therefore, to test byte and halfword load/store
+# opcodes some memory must be reserved in the DRAM segment.  This also happens
+# to work on the ESP32 too.
 
 BYTE_DATA = array.array("B", (0x11, 0x22, 0x33, 0x44))
 WORD_DATA = array.array("h", (100, 200, -100, -200))
@@ -29,8 +30,10 @@ def tl32r() -> int:
 @micropython.asm_xtensa
 def tl32i() -> uint:
     call0(ENTRY)
+    align(4)
     label(ENTRY)
     l32i(a2, a0, 0)
+    nop()
 
 
 print(hex(tl32i()))

tests/inlineasm/xtensa/asmloadstore.py.exp

@@ -1,5 +1,5 @@
 0x4030201
-0xf8002022
+0xf0002022
 0x22
 200
 -200