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Commit 135ffe5

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Remove down.denied from TL cache
1 parent c0039ce commit 135ffe5

1 file changed

Lines changed: 1 addition & 1 deletion

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  • lib/src/main/scala/spinal/lib/bus/tilelink/coherent

lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Cache.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1806,7 +1806,7 @@ class Cache(val p : CacheParam) extends Component {
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toUpD.source := CTX.sourceId
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toUpD.sink := CMD.source.resized
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toUpD.size := CTX.size
1809-
toUpD.denied := CMD.denied
1809+
toUpD.denied := False
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toUpD.data := CMD.data
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toUpD.corrupt := CMD.corrupt
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