From a49592e043767841118867d2da7aa80da21272e6 Mon Sep 17 00:00:00 2001 From: Henry Barnes Date: Sun, 1 Mar 2026 10:39:53 +0000 Subject: [PATCH 1/3] content(hardware): Add Catalyst N1 & N2 neuromorphic processors Add hardware entry for Catalyst N1 and N2, open-architecture FPGA neuromorphic processors by Catalyst Neuromorphic Ltd. Features include 128 cores, 131K neurons, CSR synapses, STDP/3-factor learning, and (N2) programmable neuron microcode with Loihi 1/2 feature parity. --- .../catalyst-neuromorphic.png | Bin 0 -> 1545 bytes .../index.md | 123 ++++++++++++++++++ 2 files changed, 123 insertions(+) create mode 100644 content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/catalyst-neuromorphic.png create mode 100644 content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md diff --git a/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/catalyst-neuromorphic.png b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/catalyst-neuromorphic.png new file mode 100644 index 0000000000000000000000000000000000000000..4a6628cca5b3ada18e36be66693ab4d6ab003ec1 GIT binary patch literal 1545 zcmeAS@N?(olHy`uVBq!ia0y~yU|a&i985rwk9x|2D{4D?g literal 0 HcmV?d00001 diff --git a/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md new file mode 100644 index 00000000..522ce952 --- /dev/null +++ b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md @@ -0,0 +1,123 @@ +--- +active_product: true +title: "Catalyst N1 & N2 - Catalyst Neuromorphic" +description: "Explore Catalyst N1 and N2 by Catalyst Neuromorphic, open-architecture FPGA neuromorphic processors with full Loihi 1/2 feature parity, 128 cores, 131K neurons, on-chip learning, and programmable neuron microcode." +type: neuromorphic-hardware +image: catalyst-neuromorphic.png +organization: + group_name: null + org_logo: catalyst-neuromorphic.png + org_name: Catalyst Neuromorphic + org_website: https://catalyst-neuromorphic.com + product_page_link: https://github.com/catalyst-neuromorphic/catalyst-neurocore + social_media_links: + linkedin: null + twitter: null + wikipedia: null +product: + announced_date: "2026-02-01" + applications: Research, Edge AI, SNN Benchmarking, Neuromorphic Algorithm Development + chip_type: Digital + neurons: "131,072 (128 cores x 1024 neurons)" + synapses: "134 million max (CSR sparse + convolutional)" + weight_bits: "1-8 bit configurable" + activation_bits: "24-bit neuron state" + on_chip_learning: true + power: null + release_year: 2026 + release_date: "2026-02-01" + software: NeuroCore SDK + status: + announced: true + released: true + retired: false +product_name: Catalyst N1 & N2 +summary: Catalyst N1 and N2 are open-architecture FPGA neuromorphic processors achieving full feature parity with Intel's Loihi 1 and Loihi 2, respectively. Deployed on Xilinx VU47P FPGAs, they feature 128 neurosynaptic cores, 131K neurons, CSR sparse synapses, STDP and three-factor learning rules, and (N2 only) programmable neuron microcode supporting five neuron models. Published benchmarks include 90.7% on SHD, 99.2% on N-MNIST, and 88.0% on Google Speech Commands. +--- + +## Overview + +Catalyst N1 and N2 are digital neuromorphic processors designed and implemented by Henry Shulayev Barnes at Catalyst Neuromorphic Ltd. Rather than targeting ASIC fabrication, both processors are deployed as FPGA-based accelerators on the Xilinx Virtex UltraScale+ VU47P, targeting AWS F2 FPGA instances for cloud-accessible neuromorphic computing. + +The Catalyst N1 achieves full feature parity with Intel's Loihi 1 processor, implementing 128 neurosynaptic cores with CUBA LIF neurons, compressed sparse row (CSR) synapses, spike-timing-dependent plasticity (STDP), three-factor learning rules, and programmable axonal delays. The Catalyst N2 extends this with full Loihi 2 feature parity, adding a programmable neuron microcode engine, graded spikes, convolutional synapse support, and five built-in neuron models. + +Both processors are accessible through the NeuroCore SDK (Python) and via a cloud API, enabling researchers to run spiking neural network workloads without dedicated neuromorphic hardware. + +## Architecture + +### Core Architecture (N1 and N2) + +Each Catalyst processor contains 128 fully digital neurosynaptic cores connected by a hierarchical mesh network-on-chip (NoC). Each core implements: + +- **1,024 neurons** with configurable parameters (threshold, decay, refractory period, bias) +- **1,024 synapse rows** using compressed sparse row (CSR) encoding for memory-efficient sparse connectivity +- **Configurable weight precision** from 1-bit to 8-bit per synapse group +- **Programmable axonal delays** (1-63 timesteps) via delay queues +- **Dendritic compartment trees** for hierarchical signal integration + +The NoC supports spike routing across all 128 cores using a hierarchical addressing scheme with configurable multicast fan-out. + +### On-Chip Learning + +Both N1 and N2 implement hardware-accelerated on-chip learning: + +- **STDP** (spike-timing-dependent plasticity) with configurable time constants +- **Three-factor learning rules** incorporating a reward/modulatory signal +- **Per-synapse-group plasticity configuration** allowing mixed learning and inference within the same network +- **Pre- and post-synaptic trace registers** updated in hardware each timestep + +### N2 Extensions + +The Catalyst N2 adds several features achieving Loihi 2 parity: + +- **Programmable neuron microcode engine**: user-defined neuron dynamics via a microcode instruction set, enabling arbitrary spiking behaviors beyond fixed LIF +- **Five built-in neuron models**: CUBA LIF, Izhikevich, Adaptive LIF (adLIF), Sigma-Delta, and Resonate-and-Fire +- **Graded spikes**: neurons can emit multi-bit payloads (up to 24-bit), not just binary spikes +- **Convolutional synapse encoding**: shared-weight convolution kernels for efficient spatial feature extraction +- **Variable-precision weights**: per-group weight bit-width selection (1, 2, 4, or 8 bits) +- **Homeostatic threshold adaptation**: activity-dependent threshold modulation for network stability + +### FPGA Implementation + +- **Target device**: Xilinx Virtex UltraScale+ VU47P (AWS F2 FPGA instances) +- **Clock frequency**: 83.3 MHz +- **Interface**: AXI4 for host communication, custom DMA for spike I/O +- **Verification**: N1 passes 96/96 tests; N2 passes 3,091 tests with 28/28 FPGA integration tests + +## Software and Tools + +Both processors are programmed through the **NeuroCore SDK**, a Python library that provides: + +- High-level network construction API (neurons, synapses, probes, learning rules) +- Compilation to hardware-native configuration +- CPU, GPU, and FPGA execution backends +- Real-time monitoring and spike raster visualization + +Additionally, a **cloud API** at [api.catalyst-neuromorphic.com](https://api.catalyst-neuromorphic.com) enables remote access to FPGA-deployed Catalyst processors without local hardware, with a Python client library available on PyPI (`catalyst-cloud`). + +## Benchmarks + +Published benchmark results on standard neuromorphic datasets: + +| Benchmark | Dataset | Accuracy | Notes | +|-----------|---------|----------|-------| +| Spiking Heidelberg Digits (SHD) | Spoken digits | 90.7% | Temporal classification | +| Spiking Speech Commands (SSC) | Speech commands | 72.1% | Large-scale temporal | +| Neuromorphic MNIST (N-MNIST) | Event-based digits | 99.2% | Spatial classification | +| Google Speech Commands (KWS) | Keyword spotting | 88.0% | Real-time audio | + +## Related Publications + +| Date | Title | Authors | Venue/Source | +|------|-------|---------|--------------| +| February 2026 | [Catalyst N1: A 128-Core Neuromorphic Processor with Full Loihi Feature Parity](https://doi.org/10.5281/zenodo.18727094) | Henry Shulayev Barnes | Zenodo | +| February 2026 | [Catalyst N2: Programmable Neuron Microcode and Loihi 2 Feature Parity in an Open Neuromorphic Architecture](https://doi.org/10.5281/zenodo.18728256) | Henry Shulayev Barnes | Zenodo | + +## Availability + +Catalyst N1 and N2 are available through two channels: + +1. **Cloud API**: Researchers can access FPGA-deployed processors via the cloud API at [api.catalyst-neuromorphic.com](https://api.catalyst-neuromorphic.com) with free and paid tiers. +2. **FPGA Bitstreams**: Available for deployment on AWS F2 instances (Xilinx VU47P). Contact Catalyst Neuromorphic for licensing. + +The NeuroCore SDK is available as compiled binaries. Source code for the RTL and SDK is proprietary (BSL 1.1 licensed). The Python cloud client is open source and available on [PyPI](https://pypi.org/project/catalyst-cloud/) and [GitHub](https://github.com/catalyst-neuromorphic/catalyst-cloud-python). From 9fcd91f7b7b532a257f32711783dc4d0d9f8c6f7 Mon Sep 17 00:00:00 2001 From: Henry Barnes Date: Wed, 8 Apr 2026 14:37:31 +0100 Subject: [PATCH 2/3] Fix licensing, add N3, update benchmarks and availability --- .../index.md | 112 +++++------------- 1 file changed, 29 insertions(+), 83 deletions(-) diff --git a/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md index 522ce952..18342a69 100644 --- a/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md +++ b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md @@ -1,7 +1,6 @@ --- active_product: true -title: "Catalyst N1 & N2 - Catalyst Neuromorphic" -description: "Explore Catalyst N1 and N2 by Catalyst Neuromorphic, open-architecture FPGA neuromorphic processors with full Loihi 1/2 feature parity, 128 cores, 131K neurons, on-chip learning, and programmable neuron microcode." +description: "Open-source FPGA neuromorphic processors by Catalyst Neuromorphic" type: neuromorphic-hardware image: catalyst-neuromorphic.png organization: @@ -9,115 +8,62 @@ organization: org_logo: catalyst-neuromorphic.png org_name: Catalyst Neuromorphic org_website: https://catalyst-neuromorphic.com - product_page_link: https://github.com/catalyst-neuromorphic/catalyst-neurocore + product_page_link: https://github.com/catalyst-neuromorphic social_media_links: linkedin: null twitter: null wikipedia: null product: announced_date: "2026-02-01" - applications: Research, Edge AI, SNN Benchmarking, Neuromorphic Algorithm Development + applications: SNN research, edge inference, neuromorphic algorithm development chip_type: Digital - neurons: "131,072 (128 cores x 1024 neurons)" - synapses: "134 million max (CSR sparse + convolutional)" - weight_bits: "1-8 bit configurable" - activation_bits: "24-bit neuron state" + neurons: "131,072 (N1/N2), 196,608 (N3)" + synapses: "131,072 per core (CSR sparse)" + weight_bits: "1-8 bit (N1), 1-16 bit (N2/N3)" + activation_bits: null on_chip_learning: true power: null release_year: 2026 release_date: "2026-02-01" - software: NeuroCore SDK + software: NeuroCore SDK (Python) status: announced: true released: true retired: false -product_name: Catalyst N1 & N2 -summary: Catalyst N1 and N2 are open-architecture FPGA neuromorphic processors achieving full feature parity with Intel's Loihi 1 and Loihi 2, respectively. Deployed on Xilinx VU47P FPGAs, they feature 128 neurosynaptic cores, 131K neurons, CSR sparse synapses, STDP and three-factor learning rules, and (N2 only) programmable neuron microcode supporting five neuron models. Published benchmarks include 90.7% on SHD, 99.2% on N-MNIST, and 88.0% on Google Speech Commands. +product_name: Catalyst N1, N2 & N3 +summary: Catalyst N1, N2 and N3 are open-source FPGA neuromorphic processors implemented in Verilog and released under Apache 2.0. N1 implements 128 cores with CUBA LIF neurons, CSR synapses, STDP and three-factor learning. N2 adds a programmable neuron microcode engine with five built-in models and 1-16 bit weight precision. N3 adds TDM virtualization, an asynchronous NoC, 8 neuron models and per-tile learning. All three are validated on Zynq UltraScale+ FPGAs via Vivado 2025.2. +title: Catalyst N1, N2 & N3 - Catalyst Neuromorphic --- ## Overview -Catalyst N1 and N2 are digital neuromorphic processors designed and implemented by Henry Shulayev Barnes at Catalyst Neuromorphic Ltd. Rather than targeting ASIC fabrication, both processors are deployed as FPGA-based accelerators on the Xilinx Virtex UltraScale+ VU47P, targeting AWS F2 FPGA instances for cloud-accessible neuromorphic computing. +Catalyst N1, N2 and N3 are digital neuromorphic processors designed by Henry Shulayev Barnes at Catalyst Neuromorphic Ltd. All three are FPGA implementations (not ASICs) with full Verilog source available under Apache 2.0. -The Catalyst N1 achieves full feature parity with Intel's Loihi 1 processor, implementing 128 neurosynaptic cores with CUBA LIF neurons, compressed sparse row (CSR) synapses, spike-timing-dependent plasticity (STDP), three-factor learning rules, and programmable axonal delays. The Catalyst N2 extends this with full Loihi 2 feature parity, adding a programmable neuron microcode engine, graded spikes, convolutional synapse support, and five built-in neuron models. +N1 implements 128 neurosynaptic cores with CUBA LIF neurons, compressed sparse row synapses, STDP, three-factor learning, dendritic compartment trees, and programmable axonal delays. N2 extends this with a programmable neuron microcode engine (LIF, Izhikevich, ALIF, Sigma-Delta, Resonate-and-Fire), graded spikes, and 1-16 bit variable-precision weights. N3 adds TDM virtualization, an asynchronous NoC, 8 neuron models, and per-tile learning engines. -Both processors are accessible through the NeuroCore SDK (Python) and via a cloud API, enabling researchers to run spiking neural network workloads without dedicated neuromorphic hardware. - -## Architecture - -### Core Architecture (N1 and N2) - -Each Catalyst processor contains 128 fully digital neurosynaptic cores connected by a hierarchical mesh network-on-chip (NoC). Each core implements: - -- **1,024 neurons** with configurable parameters (threshold, decay, refractory period, bias) -- **1,024 synapse rows** using compressed sparse row (CSR) encoding for memory-efficient sparse connectivity -- **Configurable weight precision** from 1-bit to 8-bit per synapse group -- **Programmable axonal delays** (1-63 timesteps) via delay queues -- **Dendritic compartment trees** for hierarchical signal integration - -The NoC supports spike routing across all 128 cores using a hierarchical addressing scheme with configurable multicast fan-out. - -### On-Chip Learning - -Both N1 and N2 implement hardware-accelerated on-chip learning: - -- **STDP** (spike-timing-dependent plasticity) with configurable time constants -- **Three-factor learning rules** incorporating a reward/modulatory signal -- **Per-synapse-group plasticity configuration** allowing mixed learning and inference within the same network -- **Pre- and post-synaptic trace registers** updated in hardware each timestep - -### N2 Extensions - -The Catalyst N2 adds several features achieving Loihi 2 parity: - -- **Programmable neuron microcode engine**: user-defined neuron dynamics via a microcode instruction set, enabling arbitrary spiking behaviors beyond fixed LIF -- **Five built-in neuron models**: CUBA LIF, Izhikevich, Adaptive LIF (adLIF), Sigma-Delta, and Resonate-and-Fire -- **Graded spikes**: neurons can emit multi-bit payloads (up to 24-bit), not just binary spikes -- **Convolutional synapse encoding**: shared-weight convolution kernels for efficient spatial feature extraction -- **Variable-precision weights**: per-group weight bit-width selection (1, 2, 4, or 8 bits) -- **Homeostatic threshold adaptation**: activity-dependent threshold modulation for network stability - -### FPGA Implementation - -- **Target device**: Xilinx Virtex UltraScale+ VU47P (AWS F2 FPGA instances) -- **Clock frequency**: 83.3 MHz -- **Interface**: AXI4 for host communication, custom DMA for spike I/O -- **Verification**: N1 passes 96/96 tests; N2 passes 3,091 tests with 28/28 FPGA integration tests - -## Software and Tools - -Both processors are programmed through the **NeuroCore SDK**, a Python library that provides: - -- High-level network construction API (neurons, synapses, probes, learning rules) -- Compilation to hardware-native configuration -- CPU, GPU, and FPGA execution backends -- Real-time monitoring and spike raster visualization - -Additionally, a **cloud API** at [api.catalyst-neuromorphic.com](https://api.catalyst-neuromorphic.com) enables remote access to FPGA-deployed Catalyst processors without local hardware, with a Python client library available on PyPI (`catalyst-cloud`). +Primary target is Zynq UltraScale+ (validated on ZU5EV via Vivado 2025.2, also tested on VU47P via AWS F2). Clock frequency 62.5 MHz. Programmed through the NeuroCore SDK (Python) with CPU, GPU, and FPGA backends. ## Benchmarks -Published benchmark results on standard neuromorphic datasets: +| Benchmark | Accuracy | +|-----------|----------| +| Spiking Heidelberg Digits (SHD) | 91.0% | +| Spiking Speech Commands (SSC) | 76.4% | +| Neuromorphic MNIST (N-MNIST) | 99.2% | +| Google Speech Commands (KWS) | 86.4% | -| Benchmark | Dataset | Accuracy | Notes | -|-----------|---------|----------|-------| -| Spiking Heidelberg Digits (SHD) | Spoken digits | 90.7% | Temporal classification | -| Spiking Speech Commands (SSC) | Speech commands | 72.1% | Large-scale temporal | -| Neuromorphic MNIST (N-MNIST) | Event-based digits | 99.2% | Spatial classification | -| Google Speech Commands (KWS) | Keyword spotting | 88.0% | Real-time audio | - -## Related Publications +## Related publications | Date | Title | Authors | Venue/Source | -|------|-------|---------|--------------| -| February 2026 | [Catalyst N1: A 128-Core Neuromorphic Processor with Full Loihi Feature Parity](https://doi.org/10.5281/zenodo.18727094) | Henry Shulayev Barnes | Zenodo | -| February 2026 | [Catalyst N2: Programmable Neuron Microcode and Loihi 2 Feature Parity in an Open Neuromorphic Architecture](https://doi.org/10.5281/zenodo.18728256) | Henry Shulayev Barnes | Zenodo | +|------|-------|---------|-------------| +| February 2026 | [Catalyst N1: A 128-Core Neuromorphic Processor](https://doi.org/10.5281/zenodo.18727094) | Henry Shulayev Barnes | Zenodo (preprint) | +| February 2026 | [Catalyst N2: Programmable Neuron Microcode](https://doi.org/10.5281/zenodo.18728256) | Henry Shulayev Barnes | Zenodo (preprint) | ## Availability -Catalyst N1 and N2 are available through two channels: - -1. **Cloud API**: Researchers can access FPGA-deployed processors via the cloud API at [api.catalyst-neuromorphic.com](https://api.catalyst-neuromorphic.com) with free and paid tiers. -2. **FPGA Bitstreams**: Available for deployment on AWS F2 instances (Xilinx VU47P). Contact Catalyst Neuromorphic for licensing. +All RTL source code is open source under Apache 2.0: +- [catalyst-n1](https://github.com/catalyst-neuromorphic/catalyst-n1) +- [catalyst-n2](https://github.com/catalyst-neuromorphic/catalyst-n2) +- [catalyst-n3](https://github.com/catalyst-neuromorphic/catalyst-n3) -The NeuroCore SDK is available as compiled binaries. Source code for the RTL and SDK is proprietary (BSL 1.1 licensed). The Python cloud client is open source and available on [PyPI](https://pypi.org/project/catalyst-cloud/) and [GitHub](https://github.com/catalyst-neuromorphic/catalyst-cloud-python). +Deployable on off-the-shelf Zynq UltraScale+ boards (AMD Kria KV260, KR260, ZCU104, ALINX AXU5EV-E/AXU9EG/AXU15EG). From 12a75662e340777b800b18bc92895c62f6566bb2 Mon Sep 17 00:00:00 2001 From: Henry Barnes Date: Thu, 9 Apr 2026 13:00:58 +0100 Subject: [PATCH 3/3] Add N3 paper to publications --- .../hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md | 1 + 1 file changed, 1 insertion(+) diff --git a/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md index 18342a69..2b11eedf 100644 --- a/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md +++ b/content/neuromorphic-computing/hardware/catalyst-n1-n2-catalyst-neuromorphic/index.md @@ -58,6 +58,7 @@ Primary target is Zynq UltraScale+ (validated on ZU5EV via Vivado 2025.2, also t |------|-------|---------|-------------| | February 2026 | [Catalyst N1: A 128-Core Neuromorphic Processor](https://doi.org/10.5281/zenodo.18727094) | Henry Shulayev Barnes | Zenodo (preprint) | | February 2026 | [Catalyst N2: Programmable Neuron Microcode](https://doi.org/10.5281/zenodo.18728256) | Henry Shulayev Barnes | Zenodo (preprint) | +| March 2026 | [Catalyst N3: Neuromorphic Processor Architecture](https://zenodo.org/records/18881283) | Henry Shulayev Barnes | Zenodo (preprint) | ## Availability