Adding new interface CEILR and CEILR_ER

[prafull-brcm]

Adding new electrical interface CEILR for normal reach and CEILR_ER to enable extended reach option in SERDES.

CEIMR interface is added for medium reach interconnect cable < 50cm length to connect chip to chip on same PCB.
CEILR and CEILR_ER (extended reach) interface is added to connect with cable (twin-axial copper cable backplane) < 1 m for communication interface between two cards across a backplane.
These interfaces follows OIF’s (Optical Internetworking Forum ) Common Electrical Interface.

The inteface type is set during create port using attribute SAI_PORT_ATTR_INTERFACE_TYPE and new interfaces (CEILR, CEILR_ER and CEIMR) are added to enum sai_port_interface_type_t.
Here is the ussage detail:
/**

• @brief Configure Interface type
• @type sai_port_interface_type_t
• @flags CREATE_AND_SET
• @default SAI_PORT_INTERFACE_TYPE_NONE
  */
  SAI_PORT_ATTR_INTERFACE_TYPE,

Line side attributes are set like this:
line_attr[2].id = sys_attr[2].id = SAI_PORT_ATTR_INTERFACE_TYPE;
line_attr[2].value.u32 = sys_attr[2].value.u32 = SAI_PORT_INTERFACE_TYPE_KR;

Newly added interfaces can be configured similar way:
line_attr[2].value.u32 = sys_attr[2].value.u32 = SAI_PORT_INTERFACE_TYPE_CEILR;

Call the create port using line side attribute:
rv = pai_port_apis_ptr->create_port(&line_port_id[phy_index], switch_id[phy_index],
COUNTOF(line_attr),
line_attr);

[eddyk-nvidia]

could you please clarify which technology is meant here ?

[prafull-brcm]

This is optical common electrical interface for LR as normal reach and LR_ER for extended reach backplane mode for chip to chip interface connected with copper cable for ethernet lane data rate 56G, 112G, 212G etc .

[eddyk-nvidia]

Is it some proprietary technology or standard one ?

[prafull-brcm]

CEILR is OIF standard electrical interface for backplane copper cable to connect module to module or chip to chip.

[tjchadaga]

@prafull-brcm - are you able to discuss this in the SAI community meeting on 3/12?

[prafull-brcm]

@tjchadaga I can discuss this on 3/12 meeting in SAI community meeting.

[prafull-brcm]

CEIMR interface is added for medium reach interconnect cable < 50cm length to connect chip to chip on same PCB.
CEILR and CEILR_ER (extended reach) interface is added to connect with cable (twin-axial copper cable backplane) < 1 m for communication interface between two cards across a backplane.
These interfaces follows OIF’s (Optical Internetworking Forum ) Common Electrical Interface.

[tjchadaga]

@prafull-brcm - As discussed in the community meeting, please update the PR with a detailed description of the types and usage examples

[tjchadaga]

/azp run

[azure-pipelines]

Azure Pipelines successfully started running 1 pipeline(s).

[tjchadaga]

Please also address the metachecker failure by adding CEILR & CEIMR to meta/acronyms

WARNING: Word 'CEILR' is misspelled or is acronym, add to acronyms.txt? saiport.h 513:    /** Interface type CEILR */
WARNING: Word 'CEIMR' is misspelled or is acronym, add to acronyms.txt? saiport.h 510:    /** Interface type CEIMR */

[prafull-brcm]

@tjchadaga @vmittal-msft
As discussed adding usage details for these new interfaces:
The inteface type is set during create port using attribute SAI_PORT_ATTR_INTERFACE_TYPE and new interfaces (CEILR, CEILR_ER and CEIMR) are added to enum sai_port_interface_type_t.
Here is the ussage detail:
/**
* @brief Configure Interface type
*
* @type sai_port_interface_type_t
* @flags CREATE_AND_SET
* @default SAI_PORT_INTERFACE_TYPE_NONE
*/
SAI_PORT_ATTR_INTERFACE_TYPE,

Line side attributes are set like this:
line_attr[2].id = sys_attr[2].id = SAI_PORT_ATTR_INTERFACE_TYPE;
line_attr[2].value.u32 = sys_attr[2].value.u32 = SAI_PORT_INTERFACE_TYPE_KR;

Newly added interfaces can be configured similar way:
line_attr[2].value.u32 = sys_attr[2].value.u32 = SAI_PORT_INTERFACE_TYPE_CEILR;

Call the create port using line side attribute:
rv = pai_port_apis_ptr->create_port(&line_port_id[phy_index], switch_id[phy_index],
COUNTOF(line_attr),
line_attr);

[prafull-brcm]

@vmittal-msft Updated the usage of new variable.

[tjchadaga]

@prafull-brcm - please squash your commits and force push for the metachecker to run

[tjchadaga]

@prgeor, @eddyk-nvidia - could you please help sign off on this?

[tjchadaga]

@prafull-brcm - gentle reminder to squash your commits

[prafull-brcm]

@prafull-brcm - gentle reminder to squash your commits

@tjchadaga Commits are squashed in single commit.

[apogedik]

What SAI version will this request be part of? When will the new version be released? We have customers waiting for this change.

[tjchadaga]

/azp run

[azure-pipelines]

Azure Pipelines successfully started running 1 pipeline(s).

[tjchadaga]

@prafull-brcm - could you please help place the new acronyms in the correct alphabetical order? Seeing this meta check failure

WARNING: Acronyms are not sorted: XPN, CEIMR
WARNING: Acronyms are not sorted: CEIMR, CEILR
WARNING: Acronyms are not sorted: XPN, CEIMR
WARNING: Acronyms are not sorted: CEIMR, CEILR

[tjchadaga]

What SAI version will this request be part of? When will the new version be released? We have customers waiting for this change.

@prafull-brcm, @apogedik - Since the PR is already reviewed, if the meta checker issue is resolved today, we can include it in v1.18.1 header release (to be available later today).

[prafull-brcm]

/azp run

[azure-pipelines]

Commenter does not have sufficient privileges for PR 2256 in repo opencomputeproject/SAI

[tjchadaga]

/azp run

[azure-pipelines]

Azure Pipelines successfully started running 1 pipeline(s).