From 104cdff918f43fbc195a90ca97068e3ea2ee7831 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Tue, 2 Jun 2026 14:23:33 +0200 Subject: [PATCH 01/44] 8385815: CRaC: Fix aarch64 failing testcases --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 3 +++ .../jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java | 3 ++- test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java | 10 +++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index 0aa701a2bd6..a459b507f5e 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -898,6 +898,9 @@ VM_Features VM_Version::CPUFeatures_generic() { if (_cpu_features.supports_feature(CPU_NOTPACA)) { retval.set_feature(CPU_NOTPACA); } + if (_cpu_features.supports_feature(CPU_LSE)) { + retval.set_feature(CPU_LSE); + } return retval; } diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index b75985aea1b..70e9c8d243e 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -72,7 +72,7 @@ * @requires os.arch=="aarch64" * @library /test/lib * @build SimpleCPUFeaturesTest - * @run driver jdk.test.lib.crac.CracTest 0x0 + * @run driver jdk.test.lib.crac.CracTest 0x0 -- INVALID_PACA * @run driver jdk.test.lib.crac.CracTest 0x0,0x0 -- INVALID_FORMAT1 * @run driver jdk.test.lib.crac.CracTest foobar -- INVALID_FORMAT1 */ @@ -92,6 +92,7 @@ public class SimpleCPUFeaturesTest implements CracTest { private enum ErrorMsg { INVALID_FORMAT1("must be of the form: 0xNUM"), INVALID_FORMAT2("must be of the form: 0xNUM,0xNUM"), + INVALID_PACA("For -XX:CPUFeatures, exactly one of the bits PACA (0x10000) and NOTPACA (0x100000) must be set."), MISSING_FEATURES("missing features of this CPU are"), ARCH_DOES_NOT_SUPPORT("This architecture does not support any arch-specific"), OS_DOES_NOT_SUPPORT("This OS does not support"), diff --git a/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java b/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java index 5b68e47fd0e..df0288c7cca 100644 --- a/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java @@ -42,11 +42,11 @@ * @run driver jdk.test.lib.crac.CracTest native skip fail * @run driver jdk.test.lib.crac.CracTest native skip-experimental pass * @run driver jdk.test.lib.crac.CracTest generic compatible pass - * @run driver jdk.test.lib.crac.CracTest generic exact fail-x86 + * @run driver jdk.test.lib.crac.CracTest generic exact fail-x86aarch64 * @run driver jdk.test.lib.crac.CracTest generic skip fail * @run driver jdk.test.lib.crac.CracTest generic skip-experimental pass - * @run driver jdk.test.lib.crac.CracTest ignore compatible fail-x86 - * @run driver jdk.test.lib.crac.CracTest ignore exact fail-x86 + * @run driver jdk.test.lib.crac.CracTest ignore compatible fail-x86aarch64 + * @run driver jdk.test.lib.crac.CracTest ignore exact fail-x86aarch64 * @run driver jdk.test.lib.crac.CracTest ignore skip fail * @run driver jdk.test.lib.crac.CracTest ignore skip-experimental pass */ @@ -63,8 +63,8 @@ public class CheckCPUFeaturesTest implements CracTest { @Override public void test() throws Exception { boolean success = "pass".equals(result); - if (!Platform.isX86() && !Platform.isX64()) { - success = success || "fail-x86".equals(result); + if (!Platform.isX86() && !Platform.isX64() && !Platform.isAArch64()) { + success = success || "fail-x86aarch64".equals(result); } CracBuilder builder = new CracBuilder().engine(CracEngine.PAUSE); From 6c349cde7c90b849d3503585cc976f228cfdf8d8 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 8 Jun 2026 13:58:46 +0200 Subject: [PATCH 02/44] Unify glibc features numbering --- .../cpu/aarch64/vm_version_aarch64.cpp | 19 +- .../cpu/aarch64/vm_version_aarch64.hpp | 52 ++--- src/hotspot/cpu/x86/vm_version_x86.hpp | 185 +++++++++--------- .../jdk/crac/CPUFeatures/CPUFeaturesAWS.sh | 22 +-- 4 files changed, 134 insertions(+), 144 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index a459b507f5e..600a8b4806d 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -59,8 +59,6 @@ GLIBC_UNSUPPORTED(SVEBITPERM); \ GLIBC_UNSUPPORTED(SVE2 ); \ GLIBC_UNSUPPORTED(A53MAC ); \ - GLIBC_UNSUPPORTED(ECV ); \ - GLIBC_UNSUPPORTED(WFXT ); \ GLIBC_UNSUPPORTED(NOTPACA ); \ /**/ #include "runtime/abstract_vm_version.inline.hpp" @@ -888,20 +886,9 @@ bool VM_Version::cpu_features_binary(VM_Version::VM_Features *data) { } VM_Features VM_Version::CPUFeatures_generic() { - VM_Features retval; - retval.set_feature(CPU_FP); - retval.set_feature(CPU_ASIMD); - // PACA cannot be made compatible between CPUs that do and do not support it. - if (_cpu_features.supports_feature(CPU_PACA)) { - retval.set_feature(CPU_PACA); - } - if (_cpu_features.supports_feature(CPU_NOTPACA)) { - retval.set_feature(CPU_NOTPACA); - } - if (_cpu_features.supports_feature(CPU_LSE)) { - retval.set_feature(CPU_LSE); - } - return retval; + // CPU_PACA and non-PACA processors cannot share the same image. Also we cannot disable glibc using features like CPU_LSE. + vm_exit_during_initialization("-XX:CPUFeatures=generic is not available on aarch64"); + ShouldNotReachHere(); } void VM_Version::print_using_features_cr() { diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index b353d7a3560..6e8e14b2ba3 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -34,37 +34,37 @@ class VM_Feature_Flag { public: -#define CPU_FEATURE_FLAGS(decl) \ - decl(FP, fp ) \ - decl(ASIMD, asimd ) \ - decl(EVTSTRM, evtstrm ) \ - decl(AES, aes ) \ - decl(PMULL, pmull ) \ - decl(SHA1, sha1 ) \ - decl(SHA2, sha256 ) \ - decl(CRC32, crc32 ) \ - decl(LSE, lse ) \ - decl(FPHP, fphp ) \ - decl(ASIMDHP, asimdhp ) \ - decl(DCPOP, dcpop ) \ - decl(SHA3, sha3 ) \ - decl(SHA512, sha512 ) \ - decl(SVE, sve ) \ - decl(SB, sb ) \ - decl(PACA, paca ) \ - decl(SVEBITPERM, svebitperm) \ - decl(SVE2, sve2 ) \ - decl(A53MAC, a53mac ) \ - decl(ECV, ecv ) \ - decl(WFXT, wfxt ) \ - decl(NOTPACA, notpaca ) \ +#define CPU_FEATURE_FLAGS(decl) \ + decl(FP, fp, 0) \ + decl(ASIMD, asimd, 1) \ + decl(EVTSTRM, evtstrm, 2) \ + decl(AES, aes, 3) \ + decl(PMULL, pmull, 4) \ + decl(SHA1, sha1, 5) \ + decl(SHA2, sha256, 6) \ + decl(CRC32, crc32, 7) \ + decl(LSE, lse, 8) \ + decl(FPHP, fphp, 9) \ + decl(ASIMDHP, asimdhp, 10) \ + decl(DCPOP, dcpop, 11) \ + decl(SHA3, sha3, 12) \ + decl(SHA512, sha512, 13) \ + decl(SVE, sve, 14) \ + decl(SB, sb, 15) \ + decl(PACA, paca, 16) \ + decl(SVEBITPERM, svebitperm, 17) \ + decl(SVE2, sve2, 18) \ + decl(A53MAC, a53mac, 19) \ + /* These features are added for CRaC. */ \ + decl(NOTPACA, notpaca, 63) \ /**/ enum Feature_Flag { - #define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id, + #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG - MAX_CPU_FEATURES + MAX_CPU_FEATURES, + FIRST_GLIBC_FEATURE = CPU_NOTPACA }; }; diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index 82ab8a11325..f351ae46d8e 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -40,101 +40,104 @@ class VM_Feature_Flag { public: enum Feature_Flag { #define CPU_FEATURE_FLAGS(decl) \ - decl(CX8, cx8 ) /* next bits are from cpuid 1 (EDX) */ \ - decl(CMOV, cmov ) \ - decl(FXSR, fxsr ) \ - decl(HT, ht ) \ - \ - decl(MMX, mmx ) \ - decl(3DNOW_PREFETCH, 3dnowpref ) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ - /* may not necessarily support other 3dnow instructions */ \ - decl(SSE, sse ) \ - decl(SSE2, sse2 ) \ - \ - decl(SSE3, sse3 ) /* SSE3 comes from cpuid 1 (ECX) */ \ - decl(SSSE3, ssse3 ) \ - decl(SSE4A, sse4a ) \ - decl(SSE4_1, sse4.1 ) \ - \ - decl(SSE4_2, sse4.2 ) \ - decl(POPCNT, popcnt ) \ - decl(LZCNT, lzcnt ) \ - decl(TSC, tsc ) \ - \ - decl(TSCINV_BIT, tscinvbit ) \ - decl(TSCINV, tscinv ) \ - decl(AVX, avx ) \ - decl(AVX2, avx2 ) \ - \ - decl(AES, aes ) \ - decl(ERMS, erms ) /* enhanced 'rep movsb/stosb' instructions */ \ - decl(CLMUL, clmul ) /* carryless multiply for CRC */ \ - decl(BMI1, bmi1 ) \ - \ - decl(BMI2, bmi2 ) \ - decl(RTM, rtm ) /* Restricted Transactional Memory instructions */ \ - decl(ADX, adx ) \ - decl(AVX512F, avx512f ) /* AVX 512bit foundation instructions */ \ - \ - decl(AVX512DQ, avx512dq ) \ - decl(AVX512PF, avx512pf ) \ - decl(AVX512ER, avx512er ) \ - decl(AVX512CD, avx512cd ) \ - \ - decl(AVX512BW, avx512bw ) /* Byte and word vector instructions */ \ - decl(AVX512VL, avx512vl ) /* EVEX instructions with smaller vector length */ \ - decl(SHA, sha ) /* SHA instructions */ \ - decl(FMA, fma ) /* FMA instructions */ \ - \ - decl(VZEROUPPER, vzeroupper ) /* Vzeroupper instruction */ \ - decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq ) /* Vector popcount */ \ - decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq) /* Vector carryless multiplication */ \ - decl(AVX512_VAES, avx512_vaes ) /* Vector AES instruction */ \ - \ - decl(AVX512_VNNI, avx512_vnni ) /* Vector Neural Network Instructions */ \ - decl(FLUSH, clflush ) /* flush instruction */ \ - decl(FLUSHOPT, clflushopt ) /* flusopth instruction */ \ - decl(CLWB, clwb ) /* clwb instruction */ \ - \ - decl(AVX512_VBMI2, avx512_vbmi2 ) /* VBMI2 shift left double instructions */ \ - decl(AVX512_VBMI, avx512_vbmi ) /* Vector BMI instructions */ \ - decl(HV, hv ) /* Hypervisor instructions */ \ - decl(SERIALIZE, serialize ) /* CPU SERIALIZE */ \ - decl(RDTSCP, rdtscp ) /* RDTSCP instruction */ \ - decl(RDPID, rdpid ) /* RDPID instruction */ \ - decl(FSRM, fsrm ) /* Fast Short REP MOV */ \ - decl(GFNI, gfni ) /* Vector GFNI instructions */ \ - decl(AVX512_BITALG, avx512_bitalg ) /* Vector sub-word popcount and bit gather instructions */\ - decl(F16C, f16c ) /* Half-precision and single precision FP conversion instructions*/ \ - decl(PKU, pku ) /* Protection keys for user-mode pages */ \ - decl(OSPKE, ospke ) /* OS enables protection keys */ \ - decl(CET_IBT, cet_ibt ) /* Control Flow Enforcement - Indirect Branch Tracking */ \ - decl(CET_SS, cet_ss ) /* Control Flow Enforcement - Shadow Stack */ \ - decl(AVX512_IFMA, avx512_ifma ) /* Integer Vector FMA instructions*/ \ - decl(AVX_IFMA, avx_ifma ) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ - decl(APX_F, apx_f ) /* Intel Advanced Performance Extensions*/ \ - decl(SHA512, sha512 ) /* SHA512 instructions*/ \ - decl(AVX512_FP16, avx512_fp16 ) /* AVX512 FP16 ISA support*/ \ - decl(AVX10_1, avx10_1 ) /* AVX10 512 bit vector ISA Version 1 support*/ \ - decl(AVX10_2, avx10_2 ) /* AVX10 512 bit vector ISA Version 2 support*/ \ - decl(HYBRID, hybrid ) /* Hybrid architecture */ \ - decl(FMA4, fma4 ) \ - decl(MOVBE, movbe ) \ - decl(OSXSAVE, osxsave ) \ - decl(IBT, ibt ) \ - decl(SHSTK, shstk ) /* Also known as cet_ss */ \ - decl(XSAVE, xsave ) \ - decl(CMPXCHG16, cmpxchg16 ) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ - decl(LAHFSAHF, lahfsahf ) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ - decl(HTT, htt ) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ - decl(XSAVEC, xsavec ) \ - decl(AVX_Fast_Unaligned_Load, avx_fast_unaligned_load) \ + decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ + decl(CMOV, "cmov", 1) \ + decl(FXSR, "fxsr", 2) \ + decl(HT, "ht", 3) \ + \ + decl(MMX, "mmx", 4) \ + decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ + /* may not necessarily support other 3dnow instructions */ \ + decl(SSE, "sse", 6) \ + decl(SSE2, "sse2", 7) \ + \ + decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ + decl(SSSE3, "ssse3", 9 ) \ + decl(SSE4A, "sse4a", 10) \ + decl(SSE4_1, "sse4.1", 11) \ + \ + decl(SSE4_2, "sse4.2", 12) \ + decl(POPCNT, "popcnt", 13) \ + decl(LZCNT, "lzcnt", 14) \ + decl(TSC, "tsc", 15) \ + \ + decl(TSCINV_BIT, "tscinvbit", 16) \ + decl(TSCINV, "tscinv", 17) \ + decl(AVX, "avx", 18) \ + decl(AVX2, "avx2", 19) \ + \ + decl(AES, "aes", 20) \ + decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ + decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ + decl(BMI1, "bmi1", 23) \ + \ + decl(BMI2, "bmi2", 24) \ + decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ + decl(ADX, "adx", 26) \ + decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ + \ + decl(AVX512DQ, "avx512dq", 28) \ + decl(AVX512PF, "avx512pf", 29) \ + decl(AVX512ER, "avx512er", 30) \ + decl(AVX512CD, "avx512cd", 31) \ + \ + decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ + decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ + decl(SHA, "sha", 34) /* SHA instructions */ \ + decl(FMA, "fma", 35) /* FMA instructions */ \ + \ + decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ + decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ + decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ + decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ + \ + decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ + decl(FLUSH, "clflush", 41) /* flush instruction */ \ + decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ + decl(CLWB, "clwb", 43) /* clwb instruction */ \ + \ + decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ + decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ + decl(HV, "hv", 46) /* Hypervisor instructions */ \ + decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ + decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ + decl(RDPID, "rdpid", 49) /* RDPID instruction */ \ + decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ + decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \ + decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ + decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ + decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \ + decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \ + decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ + decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ + decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ + decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ + decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ + decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \ + decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ + decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ + decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ + decl(HYBRID, "hybrid", 65) /* Hybrid architecture */ \ + /* These features are added for CRaC for GLIBC_TUNABLES=glibc.cpu.hwcaps . */ \ + decl(FMA4, "fma4", 117) \ + decl(MOVBE, "movbe", 118) \ + decl(OSXSAVE, "osxsave", 119) \ + decl(IBT, "ibt", 120) \ + decl(SHSTK, "shstk", 121) /* Also known as cet_ss */ \ + decl(XSAVE, "xsave", 122) \ + decl(CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ + decl(LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ + decl(HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ + decl(XSAVEC, "xsavec", 126) \ + decl(AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ /**/ -#define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id, +#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG - MAX_CPU_FEATURES + MAX_CPU_FEATURES, + // Define a window of unused features so that adding new CPU_* upstream does not shift the GLIBC features. + FIRST_GLIBC_FEATURE = CPU_FMA4 }; }; diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh index 224f066b318..434b14ceaff 100755 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh @@ -246,6 +246,7 @@ checkpoint_restore_one() { kind=$kind_checkpoint setup snapshot="$(runssh "./CPUFeaturesAWS.sh internal_checkpoint $enginecmdline $checkpoint_args" 2>&1|tee /proc/self/fd/2)" + local r="$engine" if [ "$expectrc" = -1 ] && echo "$snapshot"|grep "$expect_error";then r="$r-PASS" else @@ -255,7 +256,6 @@ checkpoint_restore_one() { runssh "rm -rf cr;ssh -o 'UserKnownHostsFile /dev/null' -o 'StrictHostKeyChecking no' -i key $(ipaddr $kind_checkpoint) tar cf - cr|tar xf -" fi restore="$(runssh "./CPUFeaturesAWS.sh internal_restore $enginecmdline $restore_args" 2>&1|tee /proc/self/fd/2)" - local r="$engine" if echo "$restore"|grep -w RC=$expectrc && echo "$restore"|grep "$expect_error";then r="$r-PASS" else @@ -290,7 +290,7 @@ if echo "$arch"|grep -q ', x86-64, ';then # Test 2 issues: # 1: ZULU-84672: CPUFeatures: Intel/AMD image portability problem; non-contained intersection; a!=(a&b)!=b # 2: IgnoreCPUFeatures is not inherited from snapshot to restore. -checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0xfcc on checkpoint." \ +checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0x1f98 on checkpoint." \ "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" "" # Test IgnoreCPUFeatures - in this case it only works by luck. @@ -303,13 +303,13 @@ checkpoint_restore "$LINENO" t3a.micro t3.micro "1:VM option .*CPUFeatures.* is # Test printing during snapshot: "CPU features are being kept intact as requested by -XX:CPUFeatures=ignore" checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=ignore" "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" -checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc" -checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc" +checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0x1f98" +checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0x1f98" checkpoint_restore "$LINENO" m1.small t3.micro # criu FAIL: JDK-8373027: [CRaC] [CRIU] x86: FPU xsave area present, but host cpu doesn't support it -checkpoint_restore "$LINENO" t3.micro m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x380" "" +checkpoint_restore "$LINENO" t3.micro m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x300" "" checkpoint_restore "$LINENO" t3.micro t3.micro "" "-XX:CPUFeatures=native" "" @@ -320,7 +320,7 @@ checkpoint_restore "$LINENO" t3.micro t3.micro "" "-XX:CPUFeatures=generic" "" # Currently the most modern x86_64 CPU in AWS. # criu FAIL: ZULU-84505: [CRaC] [CRIU] Fix a failure for checkpoint on AWS m8i-flex.large -checkpoint_restore "$LINENO" m8i-flex.large m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x380" "" +checkpoint_restore "$LINENO" m8i-flex.large m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x300" "" # 8374491: CPUFeatures: check performance regression of AVX_Fast_Unaligned_Load lastline="$LINENO" @@ -342,14 +342,14 @@ elif echo "$arch"|grep -q ', ARM aarch64, ';then checkpoint_restore "$LINENO" a1.medium a1.medium checkpoint_restore "$LINENO" t4g.micro t4g.micro checkpoint_restore "$LINENO" a1.medium t4g.micro -checkpoint_restore "$LINENO" t4g.micro a1.medium "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x4000ff on checkpoint." -checkpoint_restore "$LINENO" t4g.micro a1.medium "-1:LSE (0x100) cannot be disabled via -XX:CPUFeatures on aarch64." "-XX:CPUFeatures=0x4000ff" "" +checkpoint_restore "$LINENO" t4g.micro a1.medium "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x80000000000000ff on checkpoint." +checkpoint_restore "$LINENO" t4g.micro a1.medium "-1:LSE (0x100) cannot be disabled via -XX:CPUFeatures on aarch64." "-XX:CPUFeatures=0x80000000000000ff" "" -checkpoint_restore "$LINENO" c7g.medium c7g.medium -checkpoint_restore "$LINENO" c8g.medium c8g.medium +# JDK-8385359: checkpoint_restore "$LINENO" c7g.medium c7g.medium +# JDK-8385359: checkpoint_restore "$LINENO" c8g.medium c8g.medium # JDK-8385359: checkpoint_restore "$LINENO" c7g.medium c8g.medium checkpoint_restore "$LINENO" c8g.medium c7g.medium "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x17fff on checkpoint." -checkpoint_restore "$LINENO" c8g.medium c7g.medium "" "-XX:CPUFeatures=0x17fff" "" +# JDK-8385359: checkpoint_restore "$LINENO" c8g.medium c7g.medium "" "-XX:CPUFeatures=0x17fff" "" checkpoint_restore "$LINENO" t4g.micro c8g.medium "1:Restore failed due to incompatible aarch64 CPU feature PACA (0x10000); these CPUs each require a separate image." checkpoint_restore "$LINENO" c8g.medium t4g.micro "1:Restore failed due to incompatible aarch64 CPU feature PACA (0x10000); these CPUs each require a separate image." From dd9a56c371602961d1e57f39b89b9b08fcfa92cb Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 8 Jun 2026 14:07:14 +0200 Subject: [PATCH 03/44] Compilation fixes --- src/hotspot/cpu/x86/vmStructs_x86.hpp | 2 +- src/hotspot/cpu/x86/vm_version_x86.cpp | 2 +- src/hotspot/share/jvmci/vmStructs_jvmci.cpp | 4 ++-- src/hotspot/share/runtime/abstract_vm_version.inline.hpp | 8 ++++++++ 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/x86/vmStructs_x86.hpp b/src/hotspot/cpu/x86/vmStructs_x86.hpp index e0fcc7d375a..b8089a6413e 100644 --- a/src/hotspot/cpu/x86/vmStructs_x86.hpp +++ b/src/hotspot/cpu/x86/vmStructs_x86.hpp @@ -46,7 +46,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT) #endif // CPU_X86_VMSTRUCTS_X86_HPP diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 7f5dd408fa7..ca307fdefac 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -144,7 +144,7 @@ int VM_Version::_stepping; bool VM_Version::_has_intel_jcc_erratum; VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; -#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name), +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name, const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp index 4a1ddf13d60..1fdf98588fd 100644 --- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp +++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp @@ -1017,7 +1017,7 @@ static_field(VM_Version, _rop_protection, bool) \ volatile_nonstatic_field(JavaFrameAnchor, _last_Java_fp, intptr_t*) -#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT) #endif @@ -1037,7 +1037,7 @@ declare_constant(frame::interpreter_frame_sender_sp_offset) \ declare_constant(frame::interpreter_frame_last_sp_offset) -#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_LONG_CPU_FEATURE_CONSTANTS \ CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT) diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index 64aac28a7cd..00689503911 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -254,6 +254,14 @@ bool VM_Version::glibc_not_using() { VM_Features all_features; all_features.set_all_features(); + if (FIRST_GLIBC_FEATURE != MAX_CPU_FEATURES) { + assert(handled.supports_feature(FIRST_GLIBC_FEATURE), "FIRST_GLIBC_FEATURE not handled"); + VM_Feature_Flag::Feature_Flag last_cpu = static_cast(static_cast(FIRST_GLIBC_FEATURE) - 1); + while (!handled.supports_feature(last_cpu)) { + all_features.clear_feature(last_cpu); + last_cpu = static_cast(static_cast(last_cpu) - 1); + } + } if (handled != all_features) { stringStream ss; ss.print_raw("internal error: Unsupported disabling of some CPU_* "); From 2d75c5d4869b7f11d634fa30f6c0371ec785b8f1 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 8 Jun 2026 14:44:13 +0200 Subject: [PATCH 04/44] aarch64 compilation fixes --- src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp | 2 +- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 2 +- src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp index a9f2d2ff2aa..2ec901f6a2e 100644 --- a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp @@ -41,7 +41,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT) #endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index 600a8b4806d..5082770291d 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -87,7 +87,7 @@ bool VM_Version::_ic_ivau_trapped; VM_Version::VM_Features VM_Version::_features; VM_Version::VM_Features VM_Version::_cpu_features; -#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name), +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name), const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 6e8e14b2ba3..f6f2977cce1 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -55,6 +55,8 @@ class VM_Feature_Flag { decl(SVEBITPERM, svebitperm, 17) \ decl(SVE2, sve2, 18) \ decl(A53MAC, a53mac, 19) \ + decl(ECV, ecv, 20) \ + decl(WFXT, wfxt, 21) \ /* These features are added for CRaC. */ \ decl(NOTPACA, notpaca, 63) \ /**/ @@ -215,7 +217,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { static const char* _features_names[]; // Feature identification -#define CPU_FEATURE_DETECTION(id, name) \ +#define CPU_FEATURE_DETECTION(id, name, bit) \ static bool supports_##name() { return supports_feature(CPU_##id); } CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION) #undef CPU_FEATURE_DETECTION From 3fee099af56bbee8d9e4f3297ad019630195d7f1 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 8 Jun 2026 15:23:50 +0200 Subject: [PATCH 05/44] Fix x86 testcases --- test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh index 434b14ceaff..88175098400 100755 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh @@ -290,7 +290,7 @@ if echo "$arch"|grep -q ', x86-64, ';then # Test 2 issues: # 1: ZULU-84672: CPUFeatures: Intel/AMD image portability problem; non-contained intersection; a!=(a&b)!=b # 2: IgnoreCPUFeatures is not inherited from snapshot to restore. -checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0x1f98 on checkpoint." \ +checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000 on checkpoint." \ "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" "" # Test IgnoreCPUFeatures - in this case it only works by luck. @@ -303,13 +303,13 @@ checkpoint_restore "$LINENO" t3a.micro t3.micro "1:VM option .*CPUFeatures.* is # Test printing during snapshot: "CPU features are being kept intact as requested by -XX:CPUFeatures=ignore" checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=ignore" "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" -checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0x1f98" -checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0x1f98" +checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000" +checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000" checkpoint_restore "$LINENO" m1.small t3.micro # criu FAIL: JDK-8373027: [CRaC] [CRIU] x86: FPU xsave area present, but host cpu doesn't support it -checkpoint_restore "$LINENO" t3.micro m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x300" "" +checkpoint_restore "$LINENO" t3.micro m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x3800000000000000" "" checkpoint_restore "$LINENO" t3.micro t3.micro "" "-XX:CPUFeatures=native" "" @@ -320,7 +320,7 @@ checkpoint_restore "$LINENO" t3.micro t3.micro "" "-XX:CPUFeatures=generic" "" # Currently the most modern x86_64 CPU in AWS. # criu FAIL: ZULU-84505: [CRaC] [CRIU] Fix a failure for checkpoint on AWS m8i-flex.large -checkpoint_restore "$LINENO" m8i-flex.large m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x300" "" +checkpoint_restore "$LINENO" m8i-flex.large m1.small "" "-XX:CPUFeatures=0x142000070bbd7,0x3800000000000000" "" # 8374491: CPUFeatures: check performance regression of AVX_Fast_Unaligned_Load lastline="$LINENO" From e485a964a94d4eed0bb2f9a19f3082761c10ad40 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 8 Jun 2026 16:17:57 +0200 Subject: [PATCH 06/44] Fix whitespace --- src/hotspot/share/runtime/abstract_vm_version.inline.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index 00689503911..a8e8c216232 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -258,7 +258,7 @@ bool VM_Version::glibc_not_using() { assert(handled.supports_feature(FIRST_GLIBC_FEATURE), "FIRST_GLIBC_FEATURE not handled"); VM_Feature_Flag::Feature_Flag last_cpu = static_cast(static_cast(FIRST_GLIBC_FEATURE) - 1); while (!handled.supports_feature(last_cpu)) { - all_features.clear_feature(last_cpu); + all_features.clear_feature(last_cpu); last_cpu = static_cast(static_cast(last_cpu) - 1); } } From efb045e816c076003466c672120b47255c96ecfc Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 28 Jun 2026 16:32:55 +0200 Subject: [PATCH 07/44] Merge fixup. --- src/hotspot/cpu/x86/vm_version_x86.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index db63a3d58cf..3306abfa263 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -126,6 +126,9 @@ /* These are handled as an exception in VM_Version::glibc_patch(). */ \ GLIBC_UNSUPPORTED(CMPXCHG16 ); \ GLIBC_UNSUPPORTED(LAHFSAHF ); \ + /* Unused fields, see the enum definition. */ \ + GLIBC_UNSUPPORTED(MMX_UNUSED ); \ + GLIBC_UNSUPPORTED(FLUSH_UNUSED ); \ /**/ #if INCLUDE_CPU_FEATURE_ACTIVE From f5375da0605fba6280e256a7d6af4c512be8c892 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 28 Jun 2026 20:24:47 +0200 Subject: [PATCH 08/44] Fix unused bits --- src/hotspot/cpu/x86/vm_version_x86.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 3306abfa263..de96c9d60ae 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3210,6 +3210,9 @@ VM_Version::VM_Features VM_Version::CpuidInfo::feature_flags() const { } } } + // Unused fields, see the enum definition. + vm_features.set_feature(CPU_MMX_UNUSED); + vm_features.set_feature(CPU_FLUSH_UNUSED); // Composite features. if (supports_tscinv_bit() && From 1b08c8aa4db1e1e8f1b711ab9a32c172f960139e Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 28 Jun 2026 20:28:30 +0200 Subject: [PATCH 09/44] Keep CPU_FEATURE_FLAGS compatible for 2 parameters --- src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp | 2 +- .../cpu/aarch64/vm_version_aarch64.cpp | 2 +- .../cpu/aarch64/vm_version_aarch64.hpp | 60 ++++--- src/hotspot/cpu/x86/vmStructs_x86.hpp | 2 +- src/hotspot/cpu/x86/vm_version_x86.cpp | 2 +- src/hotspot/cpu/x86/vm_version_x86.hpp | 162 +++++++++--------- 6 files changed, 119 insertions(+), 111 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp index 2ec901f6a2e..a9f2d2ff2aa 100644 --- a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp @@ -41,7 +41,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT) #endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index f83726103c8..8d242f757db 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -88,7 +88,7 @@ bool VM_Version::_ic_ivau_trapped; VM_Version::VM_Features VM_Version::_features; VM_Version::VM_Features VM_Version::_cpu_features; -#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name), +#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name), const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 06d6f379eb4..575fa6b6b36 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -34,37 +34,41 @@ class VM_Feature_Flag { public: -#define CPU_FEATURE_FLAGS(decl) \ - decl(FP, fp, 0) \ - decl(ASIMD, asimd, 1) \ - decl(EVTSTRM, evtstrm, 2) \ - decl(AES, aes, 3) \ - decl(PMULL, pmull, 4) \ - decl(SHA1, sha1, 5) \ - decl(SHA2, sha256, 6) \ - decl(CRC32, crc32, 7) \ - decl(LSE, lse, 8) \ - decl(FPHP, fphp, 9) \ - decl(ASIMDHP, asimdhp, 10) \ - decl(DCPOP, dcpop, 11) \ - decl(SHA3, sha3, 12) \ - decl(SHA512, sha512, 13) \ - decl(SVE, sve, 14) \ - decl(SB, sb, 15) \ - decl(PACA, paca, 16) \ - decl(SVEBITPERM, svebitperm, 17) \ - decl(SVE2, sve2, 18) \ - decl(A53MAC, a53mac, 19) \ - decl(ECV, ecv, 20) \ - decl(WFXT, wfxt, 21) \ +#define CFF_INNER(decl2, decl3, id, name, bit) decl2(id, name) decl3(id, name, bit) +#define CFF_OUTER(...) \ + CFF_INNER(__VA_ARGS__, FP, fp, 0) \ + CFF_INNER(__VA_ARGS__, ASIMD, asimd, 1) \ + CFF_INNER(__VA_ARGS__, EVTSTRM, evtstrm, 2) \ + CFF_INNER(__VA_ARGS__, AES, aes, 3) \ + CFF_INNER(__VA_ARGS__, PMULL, pmull, 4) \ + CFF_INNER(__VA_ARGS__, SHA1, sha1, 5) \ + CFF_INNER(__VA_ARGS__, SHA2, sha256, 6) \ + CFF_INNER(__VA_ARGS__, CRC32, crc32, 7) \ + CFF_INNER(__VA_ARGS__, LSE, lse, 8) \ + CFF_INNER(__VA_ARGS__, FPHP, fphp, 9) \ + CFF_INNER(__VA_ARGS__, ASIMDHP, asimdhp, 10) \ + CFF_INNER(__VA_ARGS__, DCPOP, dcpop, 11) \ + CFF_INNER(__VA_ARGS__, SHA3, sha3, 12) \ + CFF_INNER(__VA_ARGS__, SHA512, sha512, 13) \ + CFF_INNER(__VA_ARGS__, SVE, sve, 14) \ + CFF_INNER(__VA_ARGS__, SB, sb, 15) \ + CFF_INNER(__VA_ARGS__, PACA, paca, 16) \ + CFF_INNER(__VA_ARGS__, SVEBITPERM, svebitperm, 17) \ + CFF_INNER(__VA_ARGS__, SVE2, sve2, 18) \ + CFF_INNER(__VA_ARGS__, A53MAC, a53mac, 19) \ + CFF_INNER(__VA_ARGS__, ECV, ecv, 20) \ + CFF_INNER(__VA_ARGS__, WFXT, wfxt, 21) \ /* These features are added for CRaC. */ \ - decl(NOTPACA, notpaca, 63) \ + CFF_INNER(__VA_ARGS__, NOTPACA, notpaca, 63) \ /**/ +#define CFF_INNER2_NOP(id, name) +#define CFF_INNER3_NOP(id, name, bit) +#define CPU_FEATURE_FLAGS(decl2) CFF_OUTER(decl2, CFF_INNER3_NOP) enum Feature_Flag { - #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), - CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) - #undef DECLARE_CPU_FEATURE_FLAG +#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), + CFF_OUTER(CFF_INNER2_NOP, DECLARE_CPU_FEATURE_FLAG) +#undef DECLARE_CPU_FEATURE_FLAG MAX_CPU_FEATURES, FIRST_GLIBC_FEATURE = CPU_NOTPACA }; @@ -219,7 +223,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { static const char* _features_names[]; // Feature identification -#define CPU_FEATURE_DETECTION(id, name, bit) \ +#define CPU_FEATURE_DETECTION(id, name) \ static bool supports_##name() { return supports_feature(CPU_##id); } CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION) #undef CPU_FEATURE_DETECTION diff --git a/src/hotspot/cpu/x86/vmStructs_x86.hpp b/src/hotspot/cpu/x86/vmStructs_x86.hpp index 9c251bebb20..33b1f3c5e57 100644 --- a/src/hotspot/cpu/x86/vmStructs_x86.hpp +++ b/src/hotspot/cpu/x86/vmStructs_x86.hpp @@ -45,7 +45,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT) #endif // CPU_X86_VMSTRUCTS_X86_HPP diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index de96c9d60ae..c950efe86e3 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -146,7 +146,7 @@ int VM_Version::_stepping; bool VM_Version::_has_intel_jcc_erratum; VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; -#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name, +#define DECLARE_CPU_FEATURE_NAME(id, name) name, const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index 9cf69aa7738..d14f9426db4 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -41,89 +41,93 @@ class VM_Feature_Flag { /* Fields *_UNUSED are kept for backwards compatibility of the -XX:CPUFeatures mask. * They must be defined so that detection of enum contiguity does not trigger. */ -#define CPU_FEATURE_FLAGS(decl) \ - decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ - decl(CMOV, "cmov", 1) \ - decl(FXSR, "fxsr", 2) \ - decl(HT, "ht", 3) \ - decl(MMX_UNUSED, "mmx", 4) \ - decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ - decl(SSE, "sse", 6) \ - decl(SSE2, "sse2", 7) \ - decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ - decl(SSSE3, "ssse3", 9 ) \ - decl(SSE4A, "sse4a", 10) \ - decl(SSE4_1, "sse4.1", 11) \ - decl(SSE4_2, "sse4.2", 12) \ - decl(POPCNT, "popcnt", 13) \ - decl(LZCNT, "lzcnt", 14) \ - decl(TSC, "tsc", 15) \ - decl(TSCINV_BIT, "tscinvbit", 16) \ - decl(TSCINV, "tscinv", 17) \ - decl(AVX, "avx", 18) \ - decl(AVX2, "avx2", 19) \ - decl(AES, "aes", 20) \ - decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ - decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ - decl(BMI1, "bmi1", 23) \ - decl(BMI2, "bmi2", 24) \ - decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ - decl(ADX, "adx", 26) \ - decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ - decl(AVX512DQ, "avx512dq", 28) \ - decl(AVX512PF, "avx512pf", 29) \ - decl(AVX512ER, "avx512er", 30) \ - decl(AVX512CD, "avx512cd", 31) \ - decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ - decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ - decl(SHA, "sha", 34) /* SHA instructions */ \ - decl(FMA, "fma", 35) /* FMA instructions */ \ - decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ - decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ - decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ - decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ - decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ - decl(FLUSH_UNUSED, "clflush", 41) /* flush instruction */ \ - decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ - decl(CLWB, "clwb", 43) /* clwb instruction */ \ - decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ - decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ - decl(HV, "hv", 46) /* Hypervisor instructions */ \ - decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ - decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ - decl(RDPID, "rdpid", 49) /* RDPID instruction */ \ - decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ - decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \ - decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ - decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ - decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \ - decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \ - decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ - decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ - decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ - decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ - decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ - decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \ - decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ - decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ - decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ - decl(HYBRID, "hybrid", 65) /* Hybrid architecture */ \ +#define CFF_INNER(decl2, decl3, id, name, bit) decl2(id, name) decl3(id, name, bit) +#define CFF_OUTER(...) \ + CFF_INNER(__VA_ARGS__, CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ + CFF_INNER(__VA_ARGS__, CMOV, "cmov", 1) \ + CFF_INNER(__VA_ARGS__, FXSR, "fxsr", 2) \ + CFF_INNER(__VA_ARGS__, HT, "ht", 3) \ + CFF_INNER(__VA_ARGS__, MMX_UNUSED, "mmx", 4) \ + CFF_INNER(__VA_ARGS__, 3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ + CFF_INNER(__VA_ARGS__, SSE, "sse", 6) \ + CFF_INNER(__VA_ARGS__, SSE2, "sse2", 7) \ + CFF_INNER(__VA_ARGS__, SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ + CFF_INNER(__VA_ARGS__, SSSE3, "ssse3", 9 ) \ + CFF_INNER(__VA_ARGS__, SSE4A, "sse4a", 10) \ + CFF_INNER(__VA_ARGS__, SSE4_1, "sse4.1", 11) \ + CFF_INNER(__VA_ARGS__, SSE4_2, "sse4.2", 12) \ + CFF_INNER(__VA_ARGS__, POPCNT, "popcnt", 13) \ + CFF_INNER(__VA_ARGS__, LZCNT, "lzcnt", 14) \ + CFF_INNER(__VA_ARGS__, TSC, "tsc", 15) \ + CFF_INNER(__VA_ARGS__, TSCINV_BIT, "tscinvbit", 16) \ + CFF_INNER(__VA_ARGS__, TSCINV, "tscinv", 17) \ + CFF_INNER(__VA_ARGS__, AVX, "avx", 18) \ + CFF_INNER(__VA_ARGS__, AVX2, "avx2", 19) \ + CFF_INNER(__VA_ARGS__, AES, "aes", 20) \ + CFF_INNER(__VA_ARGS__, ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ + CFF_INNER(__VA_ARGS__, CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ + CFF_INNER(__VA_ARGS__, BMI1, "bmi1", 23) \ + CFF_INNER(__VA_ARGS__, BMI2, "bmi2", 24) \ + CFF_INNER(__VA_ARGS__, RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ + CFF_INNER(__VA_ARGS__, ADX, "adx", 26) \ + CFF_INNER(__VA_ARGS__, AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ + CFF_INNER(__VA_ARGS__, AVX512DQ, "avx512dq", 28) \ + CFF_INNER(__VA_ARGS__, AVX512PF, "avx512pf", 29) \ + CFF_INNER(__VA_ARGS__, AVX512ER, "avx512er", 30) \ + CFF_INNER(__VA_ARGS__, AVX512CD, "avx512cd", 31) \ + CFF_INNER(__VA_ARGS__, AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ + CFF_INNER(__VA_ARGS__, AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ + CFF_INNER(__VA_ARGS__, SHA, "sha", 34) /* SHA instructions */ \ + CFF_INNER(__VA_ARGS__, FMA, "fma", 35) /* FMA instructions */ \ + CFF_INNER(__VA_ARGS__, VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ + CFF_INNER(__VA_ARGS__, AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ + CFF_INNER(__VA_ARGS__, AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ + CFF_INNER(__VA_ARGS__, AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ + CFF_INNER(__VA_ARGS__, AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ + CFF_INNER(__VA_ARGS__, FLUSH_UNUSED, "clflush", 41) /* flush instruction */ \ + CFF_INNER(__VA_ARGS__, FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ + CFF_INNER(__VA_ARGS__, CLWB, "clwb", 43) /* clwb instruction */ \ + CFF_INNER(__VA_ARGS__, AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ + CFF_INNER(__VA_ARGS__, AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ + CFF_INNER(__VA_ARGS__, HV, "hv", 46) /* Hypervisor instructions */ \ + CFF_INNER(__VA_ARGS__, SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ + CFF_INNER(__VA_ARGS__, RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ + CFF_INNER(__VA_ARGS__, RDPID, "rdpid", 49) /* RDPID instruction */ \ + CFF_INNER(__VA_ARGS__, FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ + CFF_INNER(__VA_ARGS__, GFNI, "gfni", 51) /* Vector GFNI instructions */ \ + CFF_INNER(__VA_ARGS__, AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ + CFF_INNER(__VA_ARGS__, F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ + CFF_INNER(__VA_ARGS__, PKU, "pku", 54) /* Protection keys for user-mode pages */ \ + CFF_INNER(__VA_ARGS__, OSPKE, "ospke", 55) /* OS enables protection keys */ \ + CFF_INNER(__VA_ARGS__, CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ + CFF_INNER(__VA_ARGS__, CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ + CFF_INNER(__VA_ARGS__, AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ + CFF_INNER(__VA_ARGS__, AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ + CFF_INNER(__VA_ARGS__, APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ + CFF_INNER(__VA_ARGS__, SHA512, "sha512", 61) /* SHA512 instructions*/ \ + CFF_INNER(__VA_ARGS__, AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ + CFF_INNER(__VA_ARGS__, AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ + CFF_INNER(__VA_ARGS__, AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ + CFF_INNER(__VA_ARGS__, HYBRID, "hybrid", 65) /* Hybrid architecture */ \ /* These features are added for CRaC for GLIBC_TUNABLES=glibc.cpu.hwcaps . */ \ - decl(FMA4, "fma4", 117) \ - decl(MOVBE, "movbe", 118) \ - decl(OSXSAVE, "osxsave", 119) \ - decl(IBT, "ibt", 120) \ - decl(SHSTK, "shstk", 121) /* Also known as cet_ss */ \ - decl(XSAVE, "xsave", 122) \ - decl(CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ - decl(LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ - decl(HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ - decl(XSAVEC, "xsavec", 126) \ - decl(AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ + CFF_INNER(__VA_ARGS__, FMA4, "fma4", 117) \ + CFF_INNER(__VA_ARGS__, MOVBE, "movbe", 118) \ + CFF_INNER(__VA_ARGS__, OSXSAVE, "osxsave", 119) \ + CFF_INNER(__VA_ARGS__, IBT, "ibt", 120) \ + CFF_INNER(__VA_ARGS__, SHSTK, "shstk", 121) /* Also known as cet_ss */ \ + CFF_INNER(__VA_ARGS__, XSAVE, "xsave", 122) \ + CFF_INNER(__VA_ARGS__, CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ + CFF_INNER(__VA_ARGS__, LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ + CFF_INNER(__VA_ARGS__, HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ + CFF_INNER(__VA_ARGS__, XSAVEC, "xsavec", 126) \ + CFF_INNER(__VA_ARGS__, AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ /**/ +#define CFF_INNER2_NOP(id, name) +#define CFF_INNER3_NOP(id, name, bit) +#define CPU_FEATURE_FLAGS(decl2) CFF_OUTER(decl2, CFF_INNER3_NOP) #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), - CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) + CFF_OUTER(CFF_INNER2_NOP, DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG MAX_CPU_FEATURES, // Define a window of unused features so that adding new CPU_* upstream does not shift the GLIBC features. From 73a7adf0a379a0d7a008ab193ce4242fde930179 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 29 Jun 2026 15:37:23 +0200 Subject: [PATCH 10/44] Revert "Keep CPU_FEATURE_FLAGS compatible for 2 parameters" This reverts commit 1b08c8aa4db1e1e8f1b711ab9a32c172f960139e. --- src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp | 2 +- .../cpu/aarch64/vm_version_aarch64.cpp | 2 +- .../cpu/aarch64/vm_version_aarch64.hpp | 60 +++---- src/hotspot/cpu/x86/vmStructs_x86.hpp | 2 +- src/hotspot/cpu/x86/vm_version_x86.cpp | 2 +- src/hotspot/cpu/x86/vm_version_x86.hpp | 162 +++++++++--------- 6 files changed, 111 insertions(+), 119 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp index a9f2d2ff2aa..2ec901f6a2e 100644 --- a/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp @@ -41,7 +41,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT) #endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index 8d242f757db..f83726103c8 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -88,7 +88,7 @@ bool VM_Version::_ic_ivau_trapped; VM_Version::VM_Features VM_Version::_features; VM_Version::VM_Features VM_Version::_cpu_features; -#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name), +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name), const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 575fa6b6b36..06d6f379eb4 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -34,41 +34,37 @@ class VM_Feature_Flag { public: -#define CFF_INNER(decl2, decl3, id, name, bit) decl2(id, name) decl3(id, name, bit) -#define CFF_OUTER(...) \ - CFF_INNER(__VA_ARGS__, FP, fp, 0) \ - CFF_INNER(__VA_ARGS__, ASIMD, asimd, 1) \ - CFF_INNER(__VA_ARGS__, EVTSTRM, evtstrm, 2) \ - CFF_INNER(__VA_ARGS__, AES, aes, 3) \ - CFF_INNER(__VA_ARGS__, PMULL, pmull, 4) \ - CFF_INNER(__VA_ARGS__, SHA1, sha1, 5) \ - CFF_INNER(__VA_ARGS__, SHA2, sha256, 6) \ - CFF_INNER(__VA_ARGS__, CRC32, crc32, 7) \ - CFF_INNER(__VA_ARGS__, LSE, lse, 8) \ - CFF_INNER(__VA_ARGS__, FPHP, fphp, 9) \ - CFF_INNER(__VA_ARGS__, ASIMDHP, asimdhp, 10) \ - CFF_INNER(__VA_ARGS__, DCPOP, dcpop, 11) \ - CFF_INNER(__VA_ARGS__, SHA3, sha3, 12) \ - CFF_INNER(__VA_ARGS__, SHA512, sha512, 13) \ - CFF_INNER(__VA_ARGS__, SVE, sve, 14) \ - CFF_INNER(__VA_ARGS__, SB, sb, 15) \ - CFF_INNER(__VA_ARGS__, PACA, paca, 16) \ - CFF_INNER(__VA_ARGS__, SVEBITPERM, svebitperm, 17) \ - CFF_INNER(__VA_ARGS__, SVE2, sve2, 18) \ - CFF_INNER(__VA_ARGS__, A53MAC, a53mac, 19) \ - CFF_INNER(__VA_ARGS__, ECV, ecv, 20) \ - CFF_INNER(__VA_ARGS__, WFXT, wfxt, 21) \ +#define CPU_FEATURE_FLAGS(decl) \ + decl(FP, fp, 0) \ + decl(ASIMD, asimd, 1) \ + decl(EVTSTRM, evtstrm, 2) \ + decl(AES, aes, 3) \ + decl(PMULL, pmull, 4) \ + decl(SHA1, sha1, 5) \ + decl(SHA2, sha256, 6) \ + decl(CRC32, crc32, 7) \ + decl(LSE, lse, 8) \ + decl(FPHP, fphp, 9) \ + decl(ASIMDHP, asimdhp, 10) \ + decl(DCPOP, dcpop, 11) \ + decl(SHA3, sha3, 12) \ + decl(SHA512, sha512, 13) \ + decl(SVE, sve, 14) \ + decl(SB, sb, 15) \ + decl(PACA, paca, 16) \ + decl(SVEBITPERM, svebitperm, 17) \ + decl(SVE2, sve2, 18) \ + decl(A53MAC, a53mac, 19) \ + decl(ECV, ecv, 20) \ + decl(WFXT, wfxt, 21) \ /* These features are added for CRaC. */ \ - CFF_INNER(__VA_ARGS__, NOTPACA, notpaca, 63) \ + decl(NOTPACA, notpaca, 63) \ /**/ -#define CFF_INNER2_NOP(id, name) -#define CFF_INNER3_NOP(id, name, bit) -#define CPU_FEATURE_FLAGS(decl2) CFF_OUTER(decl2, CFF_INNER3_NOP) enum Feature_Flag { -#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), - CFF_OUTER(CFF_INNER2_NOP, DECLARE_CPU_FEATURE_FLAG) -#undef DECLARE_CPU_FEATURE_FLAG + #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), + CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) + #undef DECLARE_CPU_FEATURE_FLAG MAX_CPU_FEATURES, FIRST_GLIBC_FEATURE = CPU_NOTPACA }; @@ -223,7 +219,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { static const char* _features_names[]; // Feature identification -#define CPU_FEATURE_DETECTION(id, name) \ +#define CPU_FEATURE_DETECTION(id, name, bit) \ static bool supports_##name() { return supports_feature(CPU_##id); } CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION) #undef CPU_FEATURE_DETECTION diff --git a/src/hotspot/cpu/x86/vmStructs_x86.hpp b/src/hotspot/cpu/x86/vmStructs_x86.hpp index 33b1f3c5e57..9c251bebb20 100644 --- a/src/hotspot/cpu/x86/vmStructs_x86.hpp +++ b/src/hotspot/cpu/x86/vmStructs_x86.hpp @@ -45,7 +45,7 @@ #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant) -#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) +#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id) #define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT) #endif // CPU_X86_VMSTRUCTS_X86_HPP diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index c950efe86e3..de96c9d60ae 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -146,7 +146,7 @@ int VM_Version::_stepping; bool VM_Version::_has_intel_jcc_erratum; VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; -#define DECLARE_CPU_FEATURE_NAME(id, name) name, +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name, const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; #undef DECLARE_CPU_FEATURE_NAME diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index d14f9426db4..9cf69aa7738 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -41,93 +41,89 @@ class VM_Feature_Flag { /* Fields *_UNUSED are kept for backwards compatibility of the -XX:CPUFeatures mask. * They must be defined so that detection of enum contiguity does not trigger. */ -#define CFF_INNER(decl2, decl3, id, name, bit) decl2(id, name) decl3(id, name, bit) -#define CFF_OUTER(...) \ - CFF_INNER(__VA_ARGS__, CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ - CFF_INNER(__VA_ARGS__, CMOV, "cmov", 1) \ - CFF_INNER(__VA_ARGS__, FXSR, "fxsr", 2) \ - CFF_INNER(__VA_ARGS__, HT, "ht", 3) \ - CFF_INNER(__VA_ARGS__, MMX_UNUSED, "mmx", 4) \ - CFF_INNER(__VA_ARGS__, 3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ - CFF_INNER(__VA_ARGS__, SSE, "sse", 6) \ - CFF_INNER(__VA_ARGS__, SSE2, "sse2", 7) \ - CFF_INNER(__VA_ARGS__, SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ - CFF_INNER(__VA_ARGS__, SSSE3, "ssse3", 9 ) \ - CFF_INNER(__VA_ARGS__, SSE4A, "sse4a", 10) \ - CFF_INNER(__VA_ARGS__, SSE4_1, "sse4.1", 11) \ - CFF_INNER(__VA_ARGS__, SSE4_2, "sse4.2", 12) \ - CFF_INNER(__VA_ARGS__, POPCNT, "popcnt", 13) \ - CFF_INNER(__VA_ARGS__, LZCNT, "lzcnt", 14) \ - CFF_INNER(__VA_ARGS__, TSC, "tsc", 15) \ - CFF_INNER(__VA_ARGS__, TSCINV_BIT, "tscinvbit", 16) \ - CFF_INNER(__VA_ARGS__, TSCINV, "tscinv", 17) \ - CFF_INNER(__VA_ARGS__, AVX, "avx", 18) \ - CFF_INNER(__VA_ARGS__, AVX2, "avx2", 19) \ - CFF_INNER(__VA_ARGS__, AES, "aes", 20) \ - CFF_INNER(__VA_ARGS__, ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ - CFF_INNER(__VA_ARGS__, CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ - CFF_INNER(__VA_ARGS__, BMI1, "bmi1", 23) \ - CFF_INNER(__VA_ARGS__, BMI2, "bmi2", 24) \ - CFF_INNER(__VA_ARGS__, RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ - CFF_INNER(__VA_ARGS__, ADX, "adx", 26) \ - CFF_INNER(__VA_ARGS__, AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ - CFF_INNER(__VA_ARGS__, AVX512DQ, "avx512dq", 28) \ - CFF_INNER(__VA_ARGS__, AVX512PF, "avx512pf", 29) \ - CFF_INNER(__VA_ARGS__, AVX512ER, "avx512er", 30) \ - CFF_INNER(__VA_ARGS__, AVX512CD, "avx512cd", 31) \ - CFF_INNER(__VA_ARGS__, AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ - CFF_INNER(__VA_ARGS__, AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ - CFF_INNER(__VA_ARGS__, SHA, "sha", 34) /* SHA instructions */ \ - CFF_INNER(__VA_ARGS__, FMA, "fma", 35) /* FMA instructions */ \ - CFF_INNER(__VA_ARGS__, VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ - CFF_INNER(__VA_ARGS__, AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ - CFF_INNER(__VA_ARGS__, AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ - CFF_INNER(__VA_ARGS__, AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ - CFF_INNER(__VA_ARGS__, AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ - CFF_INNER(__VA_ARGS__, FLUSH_UNUSED, "clflush", 41) /* flush instruction */ \ - CFF_INNER(__VA_ARGS__, FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ - CFF_INNER(__VA_ARGS__, CLWB, "clwb", 43) /* clwb instruction */ \ - CFF_INNER(__VA_ARGS__, AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ - CFF_INNER(__VA_ARGS__, AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ - CFF_INNER(__VA_ARGS__, HV, "hv", 46) /* Hypervisor instructions */ \ - CFF_INNER(__VA_ARGS__, SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ - CFF_INNER(__VA_ARGS__, RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ - CFF_INNER(__VA_ARGS__, RDPID, "rdpid", 49) /* RDPID instruction */ \ - CFF_INNER(__VA_ARGS__, FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ - CFF_INNER(__VA_ARGS__, GFNI, "gfni", 51) /* Vector GFNI instructions */ \ - CFF_INNER(__VA_ARGS__, AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ - CFF_INNER(__VA_ARGS__, F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ - CFF_INNER(__VA_ARGS__, PKU, "pku", 54) /* Protection keys for user-mode pages */ \ - CFF_INNER(__VA_ARGS__, OSPKE, "ospke", 55) /* OS enables protection keys */ \ - CFF_INNER(__VA_ARGS__, CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ - CFF_INNER(__VA_ARGS__, CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ - CFF_INNER(__VA_ARGS__, AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ - CFF_INNER(__VA_ARGS__, AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ - CFF_INNER(__VA_ARGS__, APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ - CFF_INNER(__VA_ARGS__, SHA512, "sha512", 61) /* SHA512 instructions*/ \ - CFF_INNER(__VA_ARGS__, AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ - CFF_INNER(__VA_ARGS__, AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ - CFF_INNER(__VA_ARGS__, AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ - CFF_INNER(__VA_ARGS__, HYBRID, "hybrid", 65) /* Hybrid architecture */ \ +#define CPU_FEATURE_FLAGS(decl) \ + decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ + decl(CMOV, "cmov", 1) \ + decl(FXSR, "fxsr", 2) \ + decl(HT, "ht", 3) \ + decl(MMX_UNUSED, "mmx", 4) \ + decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ + decl(SSE, "sse", 6) \ + decl(SSE2, "sse2", 7) \ + decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ + decl(SSSE3, "ssse3", 9 ) \ + decl(SSE4A, "sse4a", 10) \ + decl(SSE4_1, "sse4.1", 11) \ + decl(SSE4_2, "sse4.2", 12) \ + decl(POPCNT, "popcnt", 13) \ + decl(LZCNT, "lzcnt", 14) \ + decl(TSC, "tsc", 15) \ + decl(TSCINV_BIT, "tscinvbit", 16) \ + decl(TSCINV, "tscinv", 17) \ + decl(AVX, "avx", 18) \ + decl(AVX2, "avx2", 19) \ + decl(AES, "aes", 20) \ + decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ + decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ + decl(BMI1, "bmi1", 23) \ + decl(BMI2, "bmi2", 24) \ + decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ + decl(ADX, "adx", 26) \ + decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ + decl(AVX512DQ, "avx512dq", 28) \ + decl(AVX512PF, "avx512pf", 29) \ + decl(AVX512ER, "avx512er", 30) \ + decl(AVX512CD, "avx512cd", 31) \ + decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ + decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ + decl(SHA, "sha", 34) /* SHA instructions */ \ + decl(FMA, "fma", 35) /* FMA instructions */ \ + decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ + decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ + decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ + decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ + decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ + decl(FLUSH_UNUSED, "clflush", 41) /* flush instruction */ \ + decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ + decl(CLWB, "clwb", 43) /* clwb instruction */ \ + decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ + decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ + decl(HV, "hv", 46) /* Hypervisor instructions */ \ + decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ + decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ + decl(RDPID, "rdpid", 49) /* RDPID instruction */ \ + decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ + decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \ + decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ + decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ + decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \ + decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \ + decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ + decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ + decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ + decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ + decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ + decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \ + decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ + decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ + decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ + decl(HYBRID, "hybrid", 65) /* Hybrid architecture */ \ /* These features are added for CRaC for GLIBC_TUNABLES=glibc.cpu.hwcaps . */ \ - CFF_INNER(__VA_ARGS__, FMA4, "fma4", 117) \ - CFF_INNER(__VA_ARGS__, MOVBE, "movbe", 118) \ - CFF_INNER(__VA_ARGS__, OSXSAVE, "osxsave", 119) \ - CFF_INNER(__VA_ARGS__, IBT, "ibt", 120) \ - CFF_INNER(__VA_ARGS__, SHSTK, "shstk", 121) /* Also known as cet_ss */ \ - CFF_INNER(__VA_ARGS__, XSAVE, "xsave", 122) \ - CFF_INNER(__VA_ARGS__, CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ - CFF_INNER(__VA_ARGS__, LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ - CFF_INNER(__VA_ARGS__, HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ - CFF_INNER(__VA_ARGS__, XSAVEC, "xsavec", 126) \ - CFF_INNER(__VA_ARGS__, AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ + decl(FMA4, "fma4", 117) \ + decl(MOVBE, "movbe", 118) \ + decl(OSXSAVE, "osxsave", 119) \ + decl(IBT, "ibt", 120) \ + decl(SHSTK, "shstk", 121) /* Also known as cet_ss */ \ + decl(XSAVE, "xsave", 122) \ + decl(CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ + decl(LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ + decl(HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ + decl(XSAVEC, "xsavec", 126) \ + decl(AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ /**/ -#define CFF_INNER2_NOP(id, name) -#define CFF_INNER3_NOP(id, name, bit) -#define CPU_FEATURE_FLAGS(decl2) CFF_OUTER(decl2, CFF_INNER3_NOP) #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), - CFF_OUTER(CFF_INNER2_NOP, DECLARE_CPU_FEATURE_FLAG) + CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG MAX_CPU_FEATURES, // Define a window of unused features so that adding new CPU_* upstream does not shift the GLIBC features. From e4a3e56c977d699c12d0b3cb9be41a531fc39f9a Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 29 Jun 2026 15:40:47 +0200 Subject: [PATCH 11/44] Remove: // TODO: check if there are any mandatory features and set them here --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index f83726103c8..dce849c452e 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -887,7 +887,6 @@ bool VM_Version::cpu_features_binary(VM_Version::VM_Features *data) { } VM_Features VM_Version::CPUFeatures_mandatory() { - // TODO: check if there are any mandatory features and set them here return VM_Features(); } From ec4b5095cd8cc6c2d62dbb46cd497913e19dc3c7 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 29 Jun 2026 15:48:52 +0200 Subject: [PATCH 12/44] CPUFeaturesCheck: timeout in 1 minute --- test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.java b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.java index 6ba02b52409..e0b3e2c9c97 100644 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.java +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.java @@ -23,7 +23,7 @@ public class CPUFeaturesAWS { public static void main(String[] args) { - for (int i = 0;; ++i) { + for (int i = 0; i < 60; ++i) { System.out.println("CPUFeaturesCheck " + i); try { Thread.sleep(1000); From 7f1f37bc0cc52b06ccfaaf435f7a88374529d423 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 29 Jun 2026 22:55:49 +0200 Subject: [PATCH 13/44] Fix test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java for the new CPUFeatures generic x86_64 mask --- test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java b/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java index eb4b7efc784..2428da0097a 100644 --- a/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java +++ b/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java @@ -39,7 +39,7 @@ * @run driver jdk.test.lib.crac.CracTest */ public class CheckCPUFeaturesMessageTest implements CracTest { - private static final String GENERIC_FEATURES_X86 = "0x4067,0x0"; + private static final String GENERIC_FEATURES_X86 = "0x80c7,0x0"; private void testDefault(CracBuilder builder) throws Exception { builder.doRestoreToAnalyze() From 2f9bfa42605a5a7a4d42f344c25f4f58b2f1df58 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 29 Jun 2026 23:04:44 +0200 Subject: [PATCH 14/44] Fix test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java for the new CPUFeatures mask --- test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index c9ebb6e9b40..b6da017f789 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -52,7 +52,7 @@ * @library /test/lib * @build SimpleCPUFeaturesTest * @comment FLUSH and SSE2 must be present - * @run driver jdk.test.lib.crac.CracTest 0x60,0x0 + * @run driver jdk.test.lib.crac.CracTest 0x80c7,0x0 * @run driver jdk.test.lib.crac.CracTest foobar -- INVALID_FORMAT2 * @run driver jdk.test.lib.crac.CracTest 0xfffff,0x0 -- MISSING_FEATURES_ON_MACHINE * @run driver jdk.test.lib.crac.CracTest 0x60,0xfff -- MISSING_FEATURES_ON_MACHINE From 1383d22fafadc2d1ac5ed54402cac410009e6e58 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 1 Jul 2026 20:50:32 +0200 Subject: [PATCH 15/44] Fix _features_names --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 4 +--- src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 3 ++- src/hotspot/cpu/x86/vm_version_x86.cpp | 4 +--- src/hotspot/cpu/x86/vm_version_x86.hpp | 3 ++- .../share/runtime/vm_features.inline.hpp | 18 ++++++++++++++++++ 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index dce849c452e..43788d0bc3e 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -88,9 +88,7 @@ bool VM_Version::_ic_ivau_trapped; VM_Version::VM_Features VM_Version::_features; VM_Version::VM_Features VM_Version::_cpu_features; -#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name), -const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; -#undef DECLARE_CPU_FEATURE_NAME +const std::array VM_Version::_features_names = VM_Features::make_features_names(); static SpinWait get_spin_wait_desc() { SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount, OnSpinWaitDelay); diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 06d6f379eb4..2c839b0457c 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -26,6 +26,7 @@ #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP #define CPU_AARCH64_VM_VERSION_AARCH64_HPP +#include #include "spin_wait_aarch64.hpp" #include "runtime/abstract_vm_version.hpp" #include "utilities/sizes.hpp" @@ -216,7 +217,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { static void cpu_features_init(); - static const char* _features_names[]; + static const std::array _features_names; // Feature identification #define CPU_FEATURE_DETECTION(id, name, bit) \ diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index de96c9d60ae..386771342c3 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -146,9 +146,7 @@ int VM_Version::_stepping; bool VM_Version::_has_intel_jcc_erratum; VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; -#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name, -const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)}; -#undef DECLARE_CPU_FEATURE_NAME +const std::array VM_Version::_features_names = VM_Features::make_features_names(); // Address of instruction which causes SEGV address VM_Version::_cpuinfo_segv_addr = nullptr; diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index 9cf69aa7738..a93331c29b3 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -25,6 +25,7 @@ #ifndef CPU_X86_VM_VERSION_X86_HPP #define CPU_X86_VM_VERSION_X86_HPP +#include #include "runtime/abstract_vm_version.hpp" #include "utilities/debug.hpp" #include "utilities/formatBuffer.hpp" @@ -500,7 +501,7 @@ class VM_Version : public Abstract_VM_Version, protected VM_Feature_Flag { // Original CPU feature flags vector, not affected by VM settings. static VM_Features _cpu_features; - static const char* _features_names[]; + static const std::array _features_names; static void clear_feature(Feature_Flag feature) { _features.clear_feature(feature); diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index 38754771d54..e30571687c8 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -24,6 +24,7 @@ #ifndef SHARE_RUNTIME_VM_FEATURES_INLINE_HPP #define SHARE_RUNTIME_VM_FEATURES_INLINE_HPP +#include #include "utilities/ostream.hpp" class VM_Features : protected VM_Feature_Flag { @@ -204,6 +205,23 @@ class VM_Features : protected VM_Feature_Flag { print_numbers(ss); return buf; } + + static constexpr const char *make_features_names_name(size_t i) { + switch (i) { +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) case bit: return name ; + CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME) +#undef DECLARE_CPU_FEATURE_NAME + default: + return nullptr; + } + } + template + static constexpr std::array make_features_names(std::index_sequence) { + return {{ make_features_names_name(I)... }}; + } + static constexpr std::array make_features_names() { + return make_features_names(std::make_index_sequence{}); + } }; #endif // SHARE_RUNTIME_VM_FEATURES_INLINE_HPP From df72e36eb349ef7af8d4498e7c7ebf87da5047fa Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 1 Jul 2026 21:20:15 +0200 Subject: [PATCH 16/44] Fix _features_names on aarch64 --- src/hotspot/cpu/x86/vm_version_x86.hpp | 154 +++++++++--------- .../share/runtime/vm_features.inline.hpp | 2 +- 2 files changed, 78 insertions(+), 78 deletions(-) diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index a93331c29b3..9c18e97711c 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -43,84 +43,84 @@ class VM_Feature_Flag { * They must be defined so that detection of enum contiguity does not trigger. */ #define CPU_FEATURE_FLAGS(decl) \ - decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ - decl(CMOV, "cmov", 1) \ - decl(FXSR, "fxsr", 2) \ - decl(HT, "ht", 3) \ - decl(MMX_UNUSED, "mmx", 4) \ - decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ - decl(SSE, "sse", 6) \ - decl(SSE2, "sse2", 7) \ - decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ - decl(SSSE3, "ssse3", 9 ) \ - decl(SSE4A, "sse4a", 10) \ - decl(SSE4_1, "sse4.1", 11) \ - decl(SSE4_2, "sse4.2", 12) \ - decl(POPCNT, "popcnt", 13) \ - decl(LZCNT, "lzcnt", 14) \ - decl(TSC, "tsc", 15) \ - decl(TSCINV_BIT, "tscinvbit", 16) \ - decl(TSCINV, "tscinv", 17) \ - decl(AVX, "avx", 18) \ - decl(AVX2, "avx2", 19) \ - decl(AES, "aes", 20) \ - decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ - decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ - decl(BMI1, "bmi1", 23) \ - decl(BMI2, "bmi2", 24) \ - decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ - decl(ADX, "adx", 26) \ - decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ - decl(AVX512DQ, "avx512dq", 28) \ - decl(AVX512PF, "avx512pf", 29) \ - decl(AVX512ER, "avx512er", 30) \ - decl(AVX512CD, "avx512cd", 31) \ - decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ - decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ - decl(SHA, "sha", 34) /* SHA instructions */ \ - decl(FMA, "fma", 35) /* FMA instructions */ \ - decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ - decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ - decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ - decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ - decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ - decl(FLUSH_UNUSED, "clflush", 41) /* flush instruction */ \ - decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ - decl(CLWB, "clwb", 43) /* clwb instruction */ \ - decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ - decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ - decl(HV, "hv", 46) /* Hypervisor instructions */ \ - decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ - decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ - decl(RDPID, "rdpid", 49) /* RDPID instruction */ \ - decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ - decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \ - decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ - decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ - decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \ - decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \ - decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ - decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ - decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ - decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ - decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \ - decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \ - decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \ - decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ - decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ - decl(HYBRID, "hybrid", 65) /* Hybrid architecture */ \ + decl(CX8, cx8, 0) /* next bits are from cpuid 1 (EDX) */ \ + decl(CMOV, cmov, 1) \ + decl(FXSR, fxsr, 2) \ + decl(HT, ht, 3) \ + decl(MMX_UNUSED, mmx, 4) \ + decl(3DNOW_PREFETCH, 3dnowpref, 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ + decl(SSE, sse, 6) \ + decl(SSE2, sse2, 7) \ + decl(SSE3, sse3, 8) /* SSE3 comes from cpuid 1 (ECX) */ \ + decl(SSSE3, ssse3, 9) \ + decl(SSE4A, sse4a, 10) \ + decl(SSE4_1, sse4.1, 11) \ + decl(SSE4_2, sse4.2, 12) \ + decl(POPCNT, popcnt, 13) \ + decl(LZCNT, lzcnt, 14) \ + decl(TSC, tsc, 15) \ + decl(TSCINV_BIT, tscinvbit, 16) \ + decl(TSCINV, tscinv, 17) \ + decl(AVX, avx, 18) \ + decl(AVX2, avx2, 19) \ + decl(AES, aes, 20) \ + decl(ERMS, erms, 21) /* enhanced 'rep movsb/stosb' instructions */ \ + decl(CLMUL, clmul, 22) /* carryless multiply for CRC */ \ + decl(BMI1, bmi1, 23) \ + decl(BMI2, bmi2, 24) \ + decl(RTM, rtm, 25) /* Restricted Transactional Memory instructions */ \ + decl(ADX, adx, 26) \ + decl(AVX512F, avx512f, 27) /* AVX 512bit foundation instructions */ \ + decl(AVX512DQ, avx512dq, 28) \ + decl(AVX512PF, avx512pf, 29) \ + decl(AVX512ER, avx512er, 30) \ + decl(AVX512CD, avx512cd, 31) \ + decl(AVX512BW, avx512bw, 32) /* Byte and word vector instructions */ \ + decl(AVX512VL, avx512vl, 33) /* EVEX instructions with smaller vector length */ \ + decl(SHA, sha, 34) /* SHA instructions */ \ + decl(FMA, fma, 35) /* FMA instructions */ \ + decl(VZEROUPPER, vzeroupper, 36) /* Vzeroupper instruction */ \ + decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq, 37) /* Vector popcount */ \ + decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq, 38) /* Vector carryless multiplication */ \ + decl(AVX512_VAES, avx512_vaes, 39) /* Vector AES instruction */ \ + decl(AVX512_VNNI, avx512_vnni, 40) /* Vector Neural Network Instructions */ \ + decl(FLUSH_UNUSED, clflush, 41) /* flush instruction */ \ + decl(FLUSHOPT, clflushopt, 42) /* flusopth instruction */ \ + decl(CLWB, clwb, 43) /* clwb instruction */ \ + decl(AVX512_VBMI2, avx512_vbmi2, 44) /* VBMI2 shift left double instructions */ \ + decl(AVX512_VBMI, avx512_vbmi, 45) /* Vector BMI instructions */ \ + decl(HV, hv, 46) /* Hypervisor instructions */ \ + decl(SERIALIZE, serialize, 47) /* CPU SERIALIZE */ \ + decl(RDTSCP, rdtscp, 48) /* RDTSCP instruction */ \ + decl(RDPID, rdpid, 49) /* RDPID instruction */ \ + decl(FSRM, fsrm, 50) /* Fast Short REP MOV */ \ + decl(GFNI, gfni, 51) /* Vector GFNI instructions */ \ + decl(AVX512_BITALG, avx512_bitalg, 52) /* Vector sub-word popcount and bit gather instructions */\ + decl(F16C, f16c, 53) /* Half-precision and single precision FP conversion instructions*/ \ + decl(PKU, pku, 54) /* Protection keys for user-mode pages */ \ + decl(OSPKE, ospke, 55) /* OS enables protection keys */ \ + decl(CET_IBT, cet_ibt, 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ + decl(CET_SS, cet_ss, 57) /* Control Flow Enforcement - Shadow Stack */ \ + decl(AVX512_IFMA, avx512_ifma, 58) /* Integer Vector FMA instructions*/ \ + decl(AVX_IFMA, avx_ifma, 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \ + decl(APX_F, apx_f, 60) /* Intel Advanced Performance Extensions*/ \ + decl(SHA512, sha512, 61) /* SHA512 instructions*/ \ + decl(AVX512_FP16, avx512_fp16, 62) /* AVX512 FP16 ISA support*/ \ + decl(AVX10_1, avx10_1, 63) /* AVX10 512 bit vector ISA Version 1 support*/ \ + decl(AVX10_2, avx10_2, 64) /* AVX10 512 bit vector ISA Version 2 support*/ \ + decl(HYBRID, hybrid, 65) /* Hybrid architecture */ \ /* These features are added for CRaC for GLIBC_TUNABLES=glibc.cpu.hwcaps . */ \ - decl(FMA4, "fma4", 117) \ - decl(MOVBE, "movbe", 118) \ - decl(OSXSAVE, "osxsave", 119) \ - decl(IBT, "ibt", 120) \ - decl(SHSTK, "shstk", 121) /* Also known as cet_ss */ \ - decl(XSAVE, "xsave", 122) \ - decl(CMPXCHG16, "cmpxchg16", 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ - decl(LAHFSAHF, "lahfsahf", 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ - decl(HTT, "htt", 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ - decl(XSAVEC, "xsavec", 126) \ - decl(AVX_Fast_Unaligned_Load, "avx_fast_unaligned_load", 127) \ + decl(FMA4, fma4, 117) \ + decl(MOVBE, movbe, 118) \ + decl(OSXSAVE, osxsave, 119) \ + decl(IBT, ibt, 120) \ + decl(SHSTK, shstk, 121) /* Also known as cet_ss */ \ + decl(XSAVE, xsave, 122) \ + decl(CMPXCHG16, cmpxchg16, 123) /* Also known in cpuinfo as cx16 and in glibc as cmpxchg16b */ \ + decl(LAHFSAHF, lahfsahf, 124) /* Also known in cpuinfo as lahf_lm and in glibc as lahf64_sahf64 */ \ + decl(HTT, htt, 125) /* hotspot calls it 'ht' but that is affected by threads_per_core() */ \ + decl(XSAVEC, xsavec, 126) \ + decl(AVX_Fast_Unaligned_Load, avx_fast_unaligned_load, 127) \ /**/ #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit), diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index e30571687c8..6eefa9cfe45 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -208,7 +208,7 @@ class VM_Features : protected VM_Feature_Flag { static constexpr const char *make_features_names_name(size_t i) { switch (i) { -#define DECLARE_CPU_FEATURE_NAME(id, name, bit) case bit: return name ; +#define DECLARE_CPU_FEATURE_NAME(id, name, bit) case bit: return STR(name); CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME) #undef DECLARE_CPU_FEATURE_NAME default: From 32ad1cdbcc51ef4de12d861479ac54570b7df1b4 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Fri, 3 Jul 2026 21:08:04 +0200 Subject: [PATCH 17/44] Fix _features_names for OSX --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 2 +- src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 3 +-- src/hotspot/cpu/x86/vm_version_x86.cpp | 2 +- src/hotspot/cpu/x86/vm_version_x86.hpp | 3 +-- src/hotspot/share/runtime/vm_features.inline.hpp | 15 +++++++++++++-- 5 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index 43788d0bc3e..6d55ff8b519 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -88,7 +88,7 @@ bool VM_Version::_ic_ivau_trapped; VM_Version::VM_Features VM_Version::_features; VM_Version::VM_Features VM_Version::_cpu_features; -const std::array VM_Version::_features_names = VM_Features::make_features_names(); +const VM_Features::FeaturesNames VM_Version::_features_names = VM_Features::make_features_names(); static SpinWait get_spin_wait_desc() { SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount, OnSpinWaitDelay); diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 2c839b0457c..21f4e9cd91b 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -26,7 +26,6 @@ #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP #define CPU_AARCH64_VM_VERSION_AARCH64_HPP -#include #include "spin_wait_aarch64.hpp" #include "runtime/abstract_vm_version.hpp" #include "utilities/sizes.hpp" @@ -217,7 +216,7 @@ class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { static void cpu_features_init(); - static const std::array _features_names; + static const VM_Features::FeaturesNames _features_names; // Feature identification #define CPU_FEATURE_DETECTION(id, name, bit) \ diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 386771342c3..66cc68331a9 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -146,7 +146,7 @@ int VM_Version::_stepping; bool VM_Version::_has_intel_jcc_erratum; VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; -const std::array VM_Version::_features_names = VM_Features::make_features_names(); +const VM_Features::FeaturesNames VM_Version::_features_names = VM_Features::make_features_names(); // Address of instruction which causes SEGV address VM_Version::_cpuinfo_segv_addr = nullptr; diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index 9c18e97711c..cd090c2268c 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -25,7 +25,6 @@ #ifndef CPU_X86_VM_VERSION_X86_HPP #define CPU_X86_VM_VERSION_X86_HPP -#include #include "runtime/abstract_vm_version.hpp" #include "utilities/debug.hpp" #include "utilities/formatBuffer.hpp" @@ -501,7 +500,7 @@ class VM_Version : public Abstract_VM_Version, protected VM_Feature_Flag { // Original CPU feature flags vector, not affected by VM settings. static VM_Features _cpu_features; - static const std::array _features_names; + static const VM_Features::FeaturesNames _features_names; static void clear_feature(Feature_Flag feature) { _features.clear_feature(feature); diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index 6eefa9cfe45..ec2ecbf259b 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -206,6 +206,17 @@ class VM_Features : protected VM_Feature_Flag { return buf; } + struct FeaturesNames { + const char *a[MAX_CPU_FEATURES]; + + constexpr const char *operator[](size_t i) const { + const char *retval = a[i]; + assert(i < MAX_CPU_FEATURES, "Too big CPUFeature index"); + assert(retval != nullptr, "Undefined CPUFeatures index"); + return retval; + } + }; + static constexpr const char *make_features_names_name(size_t i) { switch (i) { #define DECLARE_CPU_FEATURE_NAME(id, name, bit) case bit: return STR(name); @@ -216,10 +227,10 @@ class VM_Features : protected VM_Feature_Flag { } } template - static constexpr std::array make_features_names(std::index_sequence) { + static constexpr FeaturesNames make_features_names(std::index_sequence) { return {{ make_features_names_name(I)... }}; } - static constexpr std::array make_features_names() { + static constexpr FeaturesNames make_features_names() { return make_features_names(std::make_index_sequence{}); } }; From 19ea63473e291bb0ab63f68c9a6ea41a75812c96 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Fri, 3 Jul 2026 22:07:39 +0200 Subject: [PATCH 18/44] Fix SortIncludes --- src/hotspot/share/runtime/vm_features.inline.hpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index ec2ecbf259b..97636ab474a 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -24,9 +24,10 @@ #ifndef SHARE_RUNTIME_VM_FEATURES_INLINE_HPP #define SHARE_RUNTIME_VM_FEATURES_INLINE_HPP -#include #include "utilities/ostream.hpp" +#include + class VM_Features : protected VM_Feature_Flag { friend class VMStructs; From 61583ec6a9a1a0e05336d47c6bf2b04bb884e1a5 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Fri, 3 Jul 2026 23:04:40 +0200 Subject: [PATCH 19/44] Fix aarch64 testcases --- .../jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java | 10 ++++++++-- test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java | 7 ++++++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index b6da017f789..077280a77ea 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -28,9 +28,15 @@ * @library /test/lib * @build SimpleCPUFeaturesTest * @run driver jdk.test.lib.crac.CracTest native - * @run driver jdk.test.lib.crac.CracTest generic * @run driver jdk.test.lib.crac.CracTest ignore */ +/* + * @test id=NAMED-GENERIC + * @requires os.arch!="aarch64" + * @library /test/lib + * @build SimpleCPUFeaturesTest + * @run driver jdk.test.lib.crac.CracTest generic + */ /* * @test id=TUNABLES * @requires os.family == "linux" @@ -93,7 +99,7 @@ public class SimpleCPUFeaturesTest implements CracTest { private enum ErrorMsg { INVALID_FORMAT1("must be of the form: 0xNUM"), INVALID_FORMAT2("must be of the form: 0xNUM,0xNUM"), - INVALID_PACA("For -XX:CPUFeatures, exactly one of the bits PACA (0x10000) and NOTPACA (0x100000) must be set."), + INVALID_PACA("For -XX:CPUFeatures, exactly one of the bits PACA (0x10000) and NOTPACA (0x8000000000000000) must be set."), MISSING_FEATURES_ON_MACHINE("missing the following features required by -XX:CPUFeatures"), MISSING_FEATURES_IN_INPUT("-XX:CPUFeatures is missing mandatory features"), ARCH_DOES_NOT_SUPPORT("This architecture does not support any arch-specific"), diff --git a/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java b/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java index 09a9507d138..c60ed7a2527 100644 --- a/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/engine/CheckCPUFeaturesTest.java @@ -73,7 +73,12 @@ public void test() throws Exception { } try (var checkpoint = builder.vmOption("-XX:CPUFeatures=" + features).startCheckpoint()) { - checkpoint.waitForPausePid(); + if (Platform.isAArch64() && "generic".equals(features)) { + assertEquals(1, checkpoint.waitFor()); + return; + } else { + checkpoint.waitForPausePid(); + } builder.clearVmOptions(); if ("skip-experimental".equals(check)) { From b59fff86d2ed97334573c85392fa9d173eedf8a1 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sat, 4 Jul 2026 22:43:00 +0200 Subject: [PATCH 20/44] Fix CPUFeaturesAWS.sh --- .../share/runtime/abstract_vm_version.inline.hpp | 5 +++++ test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh | 14 +++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index 2d15277d286..5d0820fab60 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -29,6 +29,7 @@ #include "logging/log.hpp" #include "logging/logStream.hpp" #include "memory/resourceArea.hpp" +#include "runtime/perfMemory.hpp" VM_Features VM_Version::CPUFeatures_parse(const char *str) { if (str == nullptr || strcmp(str, "native") == 0) { @@ -182,6 +183,10 @@ void VM_Version::glibc_reexec() { argv[argv_used] = nullptr; #undef CMDLINE + // Delete the hsperfdata file as the new JVM will have the same PID. + // CPUFeaturesAWS.sh would fail with: Could not find any processes matching : 'CPUFeaturesAWS' + perfMemory_exit(); + #define EXEC "/proc/self/exe" execv(EXEC, argv); vm_exit_during_initialization(err_msg("Cannot re-execute " EXEC ": %m")); diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh index afd78ffe857..0da8d2e2ca7 100755 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh @@ -253,7 +253,7 @@ checkpoint_restore_one() { if [ $kind_restore != $kind_checkpoint ];then kind=$kind_restore setup - runssh "rm -rf cr;ssh -o 'UserKnownHostsFile /dev/null' -o 'StrictHostKeyChecking no' -i key $(ipaddr $kind_checkpoint) tar cf - cr|tar xf -" + runssh "rm -rf cr;ssh -o 'UserKnownHostsFile /dev/null' -o 'StrictHostKeyChecking no' -i key $(ipaddr $kind_checkpoint) tar cf - cr|sudo tar xf -" fi restore="$(runssh "./CPUFeaturesAWS.sh internal_restore $enginecmdline $restore_args" 2>&1|tee /proc/self/fd/2)" if echo "$restore"|grep -w RC=$expectrc && echo "$restore"|grep "$expect_error";then @@ -289,19 +289,19 @@ if echo "$arch"|grep -q ', x86-64, ';then # Test 2 issues: # 1: ZULU-84672: CPUFeatures: Intel/AMD image portability problem; non-contained intersection; a!=(a&b)!=b -# 2: IgnoreCPUFeatures is not inherited from snapshot to restore. +# 2: CheckCPUFeatures=skip is not inherited from snapshot to restore. checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to incompatible or missing CPU features, try using -XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000 on checkpoint." \ - "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" "" + "-XX:+UnlockExperimentalVMOptions -XX:CheckCPUFeatures=skip" "" -# Test IgnoreCPUFeatures - in this case it only works by luck. -checkpoint_restore "$LINENO" t3a.micro t3.micro "" "" "-XX:+UnlockExperimentalVMOptions -XX:+IgnoreCPUFeatures" +# CheckCPUFeatures=skip at restore skips verification of the machine features; restore succeeds just due to a luck here. +checkpoint_restore "$LINENO" t3a.micro t3.micro "" "" "-XX:+UnlockExperimentalVMOptions -XX:CheckCPUFeatures=skip" # Test the current state of things, it may be fixed in the future. checkpoint_restore "$LINENO" t3a.micro t3.micro "1:VM option .*CPUFeatures.* is not restore-settable and is not available on restore." \ "" "-XX:CPUFeatures=ignore" -# Test printing during snapshot: "CPU features are being kept intact as requested by -XX:CPUFeatures=ignore" -checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=ignore" "" +# It should also print during snapshot: "CPU features are being kept intact as requested by -XX:CPUFeatures=ignore" +checkpoint_restore "$LINENO" t3a.micro t3.micro "1:Restore failed due to wrong or missing CPU architecture (current architecture is amd64)" "-XX:CPUFeatures=ignore" "" checkpoint_restore "$LINENO" t3a.micro t3.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000" checkpoint_restore "$LINENO" t3.micro t3a.micro "" "-XX:CPUFeatures=0x21461805ddfbf7,0xfcc0000000000000" From bcd03d7f62200710736000a91eb71cd4ad1d46e4 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 6 Jul 2026 14:36:41 +0200 Subject: [PATCH 21/44] Update src/hotspot/share/runtime/vm_features.inline.hpp Co-authored-by: Timofei Pushkin --- src/hotspot/share/runtime/vm_features.inline.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index 97636ab474a..ed81d0b3f40 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -208,10 +208,10 @@ class VM_Features : protected VM_Feature_Flag { } struct FeaturesNames { - const char *a[MAX_CPU_FEATURES]; + const char *names[MAX_CPU_FEATURES]; constexpr const char *operator[](size_t i) const { - const char *retval = a[i]; + const char *retval = names[i]; assert(i < MAX_CPU_FEATURES, "Too big CPUFeature index"); assert(retval != nullptr, "Undefined CPUFeatures index"); return retval; From b3b86640a9ee41990b5b28d015546c4b3434e4e5 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 6 Jul 2026 15:34:05 +0200 Subject: [PATCH 22/44] test/jdk/jdk/crac/ignoreRestore/MissingMetadataTest.java: Add aarch64 --- test/jdk/jdk/crac/ignoreRestore/MissingMetadataTest.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/ignoreRestore/MissingMetadataTest.java b/test/jdk/jdk/crac/ignoreRestore/MissingMetadataTest.java index fd8c5fdb515..c25a5d3128b 100644 --- a/test/jdk/jdk/crac/ignoreRestore/MissingMetadataTest.java +++ b/test/jdk/jdk/crac/ignoreRestore/MissingMetadataTest.java @@ -43,7 +43,7 @@ public class MissingMetadataTest { public static void main(String[] args) throws Exception { test("criuengine", null, "Cannot open file cr/engine"); test("criuengine", "badengine", "Image format does not match"); - if (Platform.isX64()) { // Requires a platform supporting CPU features + if (Platform.isX64() || Platform.isAArch64()) { // Requires a platform supporting CPU features test("criuengine", "criuengine", "cannot open cr/tags in mode r"); } } From 2972e2e2f424f7d236dd28c36fc3fc0809896820 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 6 Jul 2026 15:46:25 +0200 Subject: [PATCH 23/44] Update src/hotspot/share/runtime/vm_features.inline.hpp Co-authored-by: Timofei Pushkin --- src/hotspot/share/runtime/vm_features.inline.hpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index ed81d0b3f40..4ff4d942da2 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -24,8 +24,15 @@ #ifndef SHARE_RUNTIME_VM_FEATURES_INLINE_HPP #define SHARE_RUNTIME_VM_FEATURES_INLINE_HPP +// No vm_features.hpp - this depends on arch-specific VM_Feature_Flag. + +#include "memory/allocation.hpp" +#include "utilities/debug.hpp" +#include "utilities/globalDefinitions.hpp" +#include "utilities/macros.hpp" #include "utilities/ostream.hpp" +#include #include class VM_Features : protected VM_Feature_Flag { From 33af019882895dd7479896bac7642de234ede538 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 8 Jul 2026 23:10:28 +0200 Subject: [PATCH 24/44] Fix assertion on test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java --- src/hotspot/share/runtime/vm_features.inline.hpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/hotspot/share/runtime/vm_features.inline.hpp b/src/hotspot/share/runtime/vm_features.inline.hpp index 4ff4d942da2..8fe9ca2894b 100644 --- a/src/hotspot/share/runtime/vm_features.inline.hpp +++ b/src/hotspot/share/runtime/vm_features.inline.hpp @@ -220,8 +220,7 @@ class VM_Features : protected VM_Feature_Flag { constexpr const char *operator[](size_t i) const { const char *retval = names[i]; assert(i < MAX_CPU_FEATURES, "Too big CPUFeature index"); - assert(retval != nullptr, "Undefined CPUFeatures index"); - return retval; + return retval ? retval : "?"; } }; From 6566d0af060dc64f1adab219a0b7f1315a678154 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 8 Jul 2026 23:10:56 +0200 Subject: [PATCH 25/44] Fix compatibility of CPUFeatures mask with older JDKs --- src/hotspot/cpu/x86/vm_version_x86.cpp | 2 ++ test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 66cc68331a9..6ca7040d7f9 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3404,6 +3404,8 @@ VM_Features VM_Version::CPUFeatures_mandatory() { VM_Features vm_features; vm_features.set_feature(CPU_SSE); vm_features.set_feature(CPU_SSE2); + // It is for compatibility of the set with older JDKs. + vm_features.set_feature(CPU_FLUSH_UNUSED); return vm_features; } diff --git a/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java b/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java index 2428da0097a..f98dbe13ad4 100644 --- a/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java +++ b/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java @@ -39,7 +39,7 @@ * @run driver jdk.test.lib.crac.CracTest */ public class CheckCPUFeaturesMessageTest implements CracTest { - private static final String GENERIC_FEATURES_X86 = "0x80c7,0x0"; + private static final String GENERIC_FEATURES_X86 = "0x200000080c7,0x0"; private void testDefault(CracBuilder builder) throws Exception { builder.doRestoreToAnalyze() From 6745562a57931d3157b5ddc3d3f6938296719e52 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Thu, 9 Jul 2026 01:23:58 +0200 Subject: [PATCH 26/44] Fix CPUFeatures gap sanity check; fix also aarch64 --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 2 ++ src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 1 + src/hotspot/cpu/x86/vm_version_x86.hpp | 1 + .../share/runtime/abstract_vm_version.inline.hpp | 12 +++++------- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index 6d55ff8b519..422ee192828 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -60,6 +60,8 @@ GLIBC_UNSUPPORTED(SVEBITPERM); \ GLIBC_UNSUPPORTED(SVE2 ); \ GLIBC_UNSUPPORTED(A53MAC ); \ + GLIBC_UNSUPPORTED(ECV ); \ + GLIBC_UNSUPPORTED(WFXT ); \ GLIBC_UNSUPPORTED(NOTPACA ); \ /**/ #include "runtime/abstract_vm_version.inline.hpp" diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 21f4e9cd91b..1edd7df60b2 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -66,6 +66,7 @@ class VM_Feature_Flag { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) #undef DECLARE_CPU_FEATURE_FLAG MAX_CPU_FEATURES, + LAST_CPU_FEATURE = CPU_WFXT, FIRST_GLIBC_FEATURE = CPU_NOTPACA }; }; diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp index cd090c2268c..85eb6b50749 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.hpp +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp @@ -127,6 +127,7 @@ class VM_Feature_Flag { #undef DECLARE_CPU_FEATURE_FLAG MAX_CPU_FEATURES, // Define a window of unused features so that adding new CPU_* upstream does not shift the GLIBC features. + LAST_CPU_FEATURE = CPU_HYBRID, FIRST_GLIBC_FEATURE = CPU_FMA4 }; }; diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index 5d0820fab60..b964938cb94 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -263,13 +263,11 @@ bool VM_Version::glibc_not_using() { VM_Features all_features; all_features.set_all_features(); - if (FIRST_GLIBC_FEATURE != MAX_CPU_FEATURES) { - assert(handled.supports_feature(FIRST_GLIBC_FEATURE), "FIRST_GLIBC_FEATURE not handled"); - VM_Feature_Flag::Feature_Flag last_cpu = static_cast(static_cast(FIRST_GLIBC_FEATURE) - 1); - while (!handled.supports_feature(last_cpu)) { - all_features.clear_feature(last_cpu); - last_cpu = static_cast(static_cast(last_cpu) - 1); - } + for (VM_Feature_Flag::Feature_Flag gapix = static_cast(static_cast(LAST_CPU_FEATURE) + 1); + gapix < FIRST_GLIBC_FEATURE; + gapix = static_cast(static_cast(gapix) + 1)) { + assert(!handled.supports_feature(gapix), "wrongly set CPUFeatures gap"); + all_features.clear_feature(gapix); } if (handled != all_features) { stringStream ss; From fcfca738406b7aacbdb8283184733310c82f9b58 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Thu, 9 Jul 2026 09:24:30 +0200 Subject: [PATCH 27/44] Fix SimpleCPUFeaturesTest.java --- test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index 077280a77ea..c17a450562d 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -58,7 +58,7 @@ * @library /test/lib * @build SimpleCPUFeaturesTest * @comment FLUSH and SSE2 must be present - * @run driver jdk.test.lib.crac.CracTest 0x80c7,0x0 + * @run driver jdk.test.lib.crac.CracTest 0x200000080c7,0x0 * @run driver jdk.test.lib.crac.CracTest foobar -- INVALID_FORMAT2 * @run driver jdk.test.lib.crac.CracTest 0xfffff,0x0 -- MISSING_FEATURES_ON_MACHINE * @run driver jdk.test.lib.crac.CracTest 0x60,0xfff -- MISSING_FEATURES_ON_MACHINE From dc6d1cbb30b5c9260057e74e7cfe009484af89b7 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Fri, 10 Jul 2026 07:09:39 +0200 Subject: [PATCH 28/44] Update CPU_SHA value --- test/hotspot/jtreg/serviceability/sa/ClhsdbLongConstant.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/hotspot/jtreg/serviceability/sa/ClhsdbLongConstant.java b/test/hotspot/jtreg/serviceability/sa/ClhsdbLongConstant.java index e0fed251f73..7fd3eb23d02 100644 --- a/test/hotspot/jtreg/serviceability/sa/ClhsdbLongConstant.java +++ b/test/hotspot/jtreg/serviceability/sa/ClhsdbLongConstant.java @@ -107,7 +107,7 @@ private static void checkForTruncation(String longConstantOutput) throws Excepti // Expected value obtained from the CPU_SHA definition in vm_version_x86.hpp checkLongValue("VM_Version::CPU_SHA ", longConstantOutput, - 33L); + 34L); } } From e56848a336f41d191aeb0f58bdd530ecd0ac030a Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 12 Jul 2026 17:20:30 +0200 Subject: [PATCH 29/44] Fix excessive error message newline --- .../os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp index cf43222a4af..5b70f7092f1 100644 --- a/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp +++ b/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp @@ -216,18 +216,14 @@ void VM_Version::check_os_cpu_info() { paca.set_feature(CPU_PACA); VM_Features notpaca; notpaca.set_feature(CPU_NOTPACA); - stringStream ss; - ss.print_cr("For -XX:CPUFeatures, exactly one of the bits PACA (%s) and NOTPACA (%s) must be set.", paca.print_numbers(), notpaca.print_numbers()); - vm_exit_during_initialization(ss.base()); + vm_exit_during_initialization(err_msg("For -XX:CPUFeatures, exactly one of the bits PACA (%s) and NOTPACA (%s) must be set.", paca.print_numbers(), notpaca.print_numbers())); } if (_cpu_features.supports_feature(CPU_LSE) && !supports_lse()) { ResourceMark rm; VM_Features lse; lse.set_feature(VM_Feature_Flag::CPU_LSE); - stringStream ss; // GLIBC_TUNABLES=glibc.cpu.hwcaps is unsupported on aarch64 - ss.print_cr("LSE (%s) cannot be disabled via -XX:CPUFeatures on aarch64.", lse.print_numbers()); - vm_exit_during_initialization(ss.base()); + vm_exit_during_initialization(err_msg("LSE (%s) cannot be disabled via -XX:CPUFeatures on aarch64.", lse.print_numbers())); } } From 4d78c6c609e16a13aaff7a3024029230b1ca430a Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 12 Jul 2026 19:30:31 +0200 Subject: [PATCH 30/44] shift the bits for jdk17 --- src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 1edd7df60b2..0c830b008e7 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -54,9 +54,10 @@ class VM_Feature_Flag { decl(PACA, paca, 16) \ decl(SVEBITPERM, svebitperm, 17) \ decl(SVE2, sve2, 18) \ - decl(A53MAC, a53mac, 19) \ - decl(ECV, ecv, 20) \ - decl(WFXT, wfxt, 21) \ + decl(STXR_PREFETCH_UNUSED, stxr_prefetch, 19) \ + decl(A53MAC, a53mac, 20) \ + decl(ECV, ecv, 21) \ + decl(WFXT, wfxt, 22) \ /* These features are added for CRaC. */ \ decl(NOTPACA, notpaca, 63) \ /**/ From 9e37a4024318c537f0150bb2a01c26351e13d02c Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 12 Jul 2026 22:44:59 +0200 Subject: [PATCH 31/44] Fix aarch64 build --- src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp index 5b70f7092f1..3f935146084 100644 --- a/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp +++ b/src/hotspot/os_cpu/linux_aarch64/vm_version_linux_aarch64.cpp @@ -28,6 +28,7 @@ #include "runtime/os.hpp" #include "runtime/os.inline.hpp" #include "runtime/vm_version.hpp" +#include "utilities/formatBuffer.hpp" #include #include From 5f99e03726347cbeb57f0a8e46eb60144f374c88 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sun, 12 Jul 2026 23:14:36 +0200 Subject: [PATCH 32/44] Fix aarch64 --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index a47d044e114..f4edda8dfef 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -59,6 +59,7 @@ GLIBC_UNSUPPORTED(PACA ); \ GLIBC_UNSUPPORTED(SVEBITPERM); \ GLIBC_UNSUPPORTED(SVE2 ); \ + GLIBC_UNSUPPORTED(STXR_PREFETCH_UNUSED); \ GLIBC_UNSUPPORTED(A53MAC ); \ GLIBC_UNSUPPORTED(ECV ); \ GLIBC_UNSUPPORTED(WFXT ); \ From e5c19cf4c2c3717c129913aebdc87382af09726d Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 13 Jul 2026 01:03:27 +0200 Subject: [PATCH 33/44] CPUFeaturesAWS.sh: Fix random shutdowns --- test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh index 0da8d2e2ca7..18a1753629a 100755 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh @@ -180,7 +180,7 @@ setup() { fi getipaddr if [ -z "$(ipaddr $kind)" ];then - aws ec2 run-instances --no-cli-pager --profile $profile --region us-west-2 --image-id $debianami --instance-type $kind --key-name $AWS_KEY_NAME --subnet-id subnet-0a6fd4c98705a4c63 --security-group-ids sg-0081bc08de42b1086 --tag-specifications "ResourceType=instance,Tags=[{Key=Name,Value=$awstagname-$kind}]" --instance-initiated-shutdown-behavior terminate --user-data $'#!/bin/bash\nshutdown -P +'$awstimeout + aws ec2 run-instances --no-cli-pager --profile $profile --region us-west-2 --image-id $debianami --instance-type $kind --key-name $AWS_KEY_NAME --subnet-id subnet-0a6fd4c98705a4c63 --security-group-ids sg-0081bc08de42b1086 --tag-specifications "ResourceType=instance,Tags=[{Key=Name,Value=$awstagname-$kind}]" --instance-initiated-shutdown-behavior terminate --user-data $'#!/bin/bash\n(sleep '$awstimeout'm;shutdown -P now)&' for i in `seq 1 60`;do getipaddr if [ -n "$(ipaddr $kind)" ];then From b48c809532684b6d84969ce8a3fa5695a4855732 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 15 Jul 2026 20:28:21 +0200 Subject: [PATCH 34/44] Sync CPU Feature with jdk26 --- src/hotspot/cpu/aarch64/vm_version_aarch64.hpp | 4 ---- src/hotspot/cpu/x86/vm_version_x86.cpp | 11 ++++++++++- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp index 0c830b008e7..c44c9124523 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -74,10 +74,6 @@ class VM_Feature_Flag { #include "runtime/vm_features.inline.hpp" -class stringStream; - -#define BIT_MASK(flag) (1ULL<<(flag)) - class VM_Version : public Abstract_VM_Version, public VM_Feature_Flag { friend class VMStructs; diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 1f9d9ad27f6..2d36ec23aea 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3201,6 +3201,14 @@ VM_Version::VM_Features VM_Version::CpuidInfo::feature_flags() const { if (std_cpuid1_ecx.bits.osxsave != 0) { vm_features.set_feature(CPU_OSXSAVE); } + if (sef_cpuid7_edx.bits.cet_ibt != 0) { + // GLIBC name for CPU_CET_IBT, we could share its bit in VM_Features. + vm_features.set_feature(CPU_IBT); + } + if (sef_cpuid7_ecx.bits.cet_ss != 0) { + // GLIBC name for CPU_CET_SS, we could share its bit in VM_Features. + vm_features.set_feature(CPU_SHSTK); + } if (std_cpuid1_ecx.bits.xsave != 0) { vm_features.set_feature(CPU_XSAVE); } @@ -3425,9 +3433,9 @@ bool VM_Version::is_intrinsic_supported(vmIntrinsicID id) { VM_Features VM_Version::CPUFeatures_mandatory() { VM_Features vm_features; - vm_features.set_feature(CPU_SSE); vm_features.set_feature(CPU_SSE2); // It is for compatibility of the set with older JDKs. + vm_features.set_feature(CPU_MMX_UNUSED); vm_features.set_feature(CPU_FLUSH_UNUSED); return vm_features; } @@ -3439,6 +3447,7 @@ VM_Features VM_Version::CPUFeatures_generic() { VM_Features retval = CPUFeatures_mandatory(); #ifdef AMD64 // The following options are all in /proc/cpuinfo of one of the first 64-bit CPUs - Atom D2700 (and Opteron 1352): https://superuser.com/q/1572306/1015048 + retval.set_feature(CPU_SSE); // enabled in 'gcc -Q --help=target', used by OpenJDK retval.set_feature(CPU_FXSR); // enabled in 'gcc -Q --help=target', not used by OpenJDK retval.set_feature(CPU_TSC); // not used by gcc, used by OpenJDK retval.set_feature(CPU_CX8); // gcc detects it to set cpu "pentium" (=32-bit only), used by OpenJDK From 9ecabed07c36fd90afe97f398f72411a7e6d9d22 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 15 Jul 2026 20:47:45 +0200 Subject: [PATCH 35/44] move/unify VM_Version::print_using_features_cr --- src/hotspot/cpu/aarch64/vm_version_aarch64.cpp | 10 ---------- src/hotspot/cpu/x86/vm_version_x86.cpp | 10 ---------- .../share/runtime/abstract_vm_version.inline.hpp | 10 ++++++++++ 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index f4edda8dfef..f07315a8637 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -905,16 +905,6 @@ VM_Features VM_Version::CPUFeatures_generic() { ShouldNotReachHere(); } -void VM_Version::print_using_features_cr() { - if (_ignore_glibc_not_using) { - tty->print_raw_cr("CPU features are being kept intact as requested by -XX:CPUFeatures=ignore"); - } else { - tty->print_raw("CPU features being used are: -XX:CPUFeatures="); - _features.print_numbers(*tty); - tty->cr(); - } -} - const char *VM_Version::restore_failed_check(const VM_Features *image_features, const VM_Features *current_features) { if (image_features->supports_feature(VM_Feature_Flag::CPU_PACA) == current_features->supports_feature(VM_Feature_Flag::CPU_PACA)) { diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 2d36ec23aea..ce019534f6e 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -2167,16 +2167,6 @@ bool VM_Version::cpu_features_binary(VM_Version::VM_Features *data) { return true; } -void VM_Version::print_using_features_cr() { - if (_ignore_glibc_not_using) { - tty->print_raw_cr("CPU features are being kept intact as requested by -XX:CPUFeatures=ignore"); - } else { - tty->print_raw("CPU features being used are: -XX:CPUFeatures="); - _features.aot_code_cache_features().print_numbers(*tty); - tty->cr(); - } -} - #ifdef COMPILER2 // Determine if it's running on Cascade Lake using default options. bool VM_Version::is_default_intel_cascade_lake() { diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index b964938cb94..5ae566c0bdb 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -289,6 +289,16 @@ bool VM_Version::glibc_not_using() { #undef REEXEC_NAME #endif // LINUX +void VM_Version::print_using_features_cr() { + if (_ignore_glibc_not_using) { + tty->print_raw_cr("CPU features are being kept intact as requested by -XX:CPUFeatures=ignore"); + } else { + tty->print_raw("CPU features being used are: -XX:CPUFeatures="); + _features.print_numbers(*tty); + tty->cr(); + } +} + void VM_Version::cpu_features_init() { assert(!CPUFeatures == FLAG_IS_DEFAULT(CPUFeatures), "CPUFeatures parsing"); assert((CPUFeatures_mandatory() & ~_features).empty(), "machine is missing mandatory features"); From 6bc10e4ab93b59d569faf92fded9a28e6d26e14d Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 15 Jul 2026 22:22:35 +0200 Subject: [PATCH 36/44] Make the mask compatible with jdk26 --- test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index c17a450562d..2bd5fb584e6 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -70,8 +70,8 @@ * @requires os.family != "linux" * @library /test/lib * @build SimpleCPUFeaturesTest - * @run driver jdk.test.lib.crac.CracTest foobar -- OS_DOES_NOT_SUPPORT - * @run driver jdk.test.lib.crac.CracTest 0x60,0x0 -- OS_DOES_NOT_SUPPORT + * @run driver jdk.test.lib.crac.CracTest foobar -- OS_DOES_NOT_SUPPORT + * @run driver jdk.test.lib.crac.CracTest 0x20000000080,0x0 -- OS_DOES_NOT_SUPPORT */ /* * @test id=AARCH64-LINUX From d2d6b5608b258664feae7dfbccb9b85a2054fdd7 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 15 Jul 2026 22:36:54 +0200 Subject: [PATCH 37/44] Fix mandatory mmx --- test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java index 2bd5fb584e6..a84f0de5aca 100644 --- a/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java +++ b/test/jdk/jdk/crac/CPUFeatures/SimpleCPUFeaturesTest.java @@ -58,7 +58,7 @@ * @library /test/lib * @build SimpleCPUFeaturesTest * @comment FLUSH and SSE2 must be present - * @run driver jdk.test.lib.crac.CracTest 0x200000080c7,0x0 + * @run driver jdk.test.lib.crac.CracTest 0x200000080d7,0x0 * @run driver jdk.test.lib.crac.CracTest foobar -- INVALID_FORMAT2 * @run driver jdk.test.lib.crac.CracTest 0xfffff,0x0 -- MISSING_FEATURES_ON_MACHINE * @run driver jdk.test.lib.crac.CracTest 0x60,0xfff -- MISSING_FEATURES_ON_MACHINE From 9234bbf048e1740b48800deee1f7a58b84dfbb6c Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Wed, 15 Jul 2026 23:40:39 +0200 Subject: [PATCH 38/44] Try to make the testcase more safe against unexpected shutdowns --- test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh index 18a1753629a..720ff3950b6 100755 --- a/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh +++ b/test/jdk/jdk/crac/CPUFeatures/CPUFeaturesAWS.sh @@ -180,7 +180,7 @@ setup() { fi getipaddr if [ -z "$(ipaddr $kind)" ];then - aws ec2 run-instances --no-cli-pager --profile $profile --region us-west-2 --image-id $debianami --instance-type $kind --key-name $AWS_KEY_NAME --subnet-id subnet-0a6fd4c98705a4c63 --security-group-ids sg-0081bc08de42b1086 --tag-specifications "ResourceType=instance,Tags=[{Key=Name,Value=$awstagname-$kind}]" --instance-initiated-shutdown-behavior terminate --user-data $'#!/bin/bash\n(sleep '$awstimeout'm;shutdown -P now)&' + aws ec2 run-instances --no-cli-pager --profile $profile --region us-west-2 --image-id $debianami --instance-type $kind --key-name $AWS_KEY_NAME --subnet-id subnet-0a6fd4c98705a4c63 --security-group-ids sg-0081bc08de42b1086 --tag-specifications "ResourceType=instance,Tags=[{Key=Name,Value=$awstagname-$kind}]" --instance-initiated-shutdown-behavior terminate --user-data $'#!/bin/bash\nfor i in $(seq 1 '$awstimeout');do sleep 1m;done;shutdown -P now' for i in `seq 1 60`;do getipaddr if [ -n "$(ipaddr $kind)" ];then From bacb940dca9912e56b17902c8a49f8b5692c03c2 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Thu, 16 Jul 2026 01:10:46 +0200 Subject: [PATCH 39/44] FIx CheckCPUFeaturesMessageTest.java --- src/hotspot/share/runtime/abstract_vm_version.inline.hpp | 2 +- test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp index 5ae566c0bdb..8f710ef642d 100644 --- a/src/hotspot/share/runtime/abstract_vm_version.inline.hpp +++ b/src/hotspot/share/runtime/abstract_vm_version.inline.hpp @@ -294,7 +294,7 @@ void VM_Version::print_using_features_cr() { tty->print_raw_cr("CPU features are being kept intact as requested by -XX:CPUFeatures=ignore"); } else { tty->print_raw("CPU features being used are: -XX:CPUFeatures="); - _features.print_numbers(*tty); + _features.aot_code_cache_features().print_numbers(*tty); tty->cr(); } } diff --git a/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java b/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java index f98dbe13ad4..c658ed48b82 100644 --- a/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java +++ b/test/jdk/jdk/crac/engine/CheckCPUFeaturesMessageTest.java @@ -39,7 +39,7 @@ * @run driver jdk.test.lib.crac.CracTest */ public class CheckCPUFeaturesMessageTest implements CracTest { - private static final String GENERIC_FEATURES_X86 = "0x200000080c7,0x0"; + private static final String GENERIC_FEATURES_X86 = "0x200000080d7,0x0"; private void testDefault(CracBuilder builder) throws Exception { builder.doRestoreToAnalyze() From fb2b917c7302f4b9628b36f76f75e3ba23bcc580 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Thu, 16 Jul 2026 19:44:31 +0200 Subject: [PATCH 40/44] Return CPU_SSE to CPUFeatures_mandatory() --- src/hotspot/cpu/x86/vm_version_x86.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index ce019534f6e..eaf3891905d 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3423,6 +3423,8 @@ bool VM_Version::is_intrinsic_supported(vmIntrinsicID id) { VM_Features VM_Version::CPUFeatures_mandatory() { VM_Features vm_features; + // SSE and SSE2 are set unconditionally in feature_flags(). + vm_features.set_feature(CPU_SSE); vm_features.set_feature(CPU_SSE2); // It is for compatibility of the set with older JDKs. vm_features.set_feature(CPU_MMX_UNUSED); @@ -3437,7 +3439,6 @@ VM_Features VM_Version::CPUFeatures_generic() { VM_Features retval = CPUFeatures_mandatory(); #ifdef AMD64 // The following options are all in /proc/cpuinfo of one of the first 64-bit CPUs - Atom D2700 (and Opteron 1352): https://superuser.com/q/1572306/1015048 - retval.set_feature(CPU_SSE); // enabled in 'gcc -Q --help=target', used by OpenJDK retval.set_feature(CPU_FXSR); // enabled in 'gcc -Q --help=target', not used by OpenJDK retval.set_feature(CPU_TSC); // not used by gcc, used by OpenJDK retval.set_feature(CPU_CX8); // gcc detects it to set cpu "pentium" (=32-bit only), used by OpenJDK From 96e0bab031f6bbbeb838fb7fa6a4f5ae75e546b8 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Thu, 16 Jul 2026 19:47:08 +0200 Subject: [PATCH 41/44] Remove unconditional setting of MMX_UNUSED and FLUSH_UNUSED as they are in *_mandatory_() --- src/hotspot/cpu/x86/vm_version_x86.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index eaf3891905d..449d669debf 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3229,9 +3229,6 @@ VM_Version::VM_Features VM_Version::CpuidInfo::feature_flags() const { } } } - // Unused fields, see the enum definition. - vm_features.set_feature(CPU_MMX_UNUSED); - vm_features.set_feature(CPU_FLUSH_UNUSED); // Composite features. if (supports_tscinv_bit() && From 31f02982f7d100dc5b9b9671f7f661ccadea129b Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Thu, 16 Jul 2026 23:11:34 +0200 Subject: [PATCH 42/44] Revert "Remove unconditional setting of MMX_UNUSED and FLUSH_UNUSED as they are in *_mandatory_()" This reverts commit 96e0bab031f6bbbeb838fb7fa6a4f5ae75e546b8. --- src/hotspot/cpu/x86/vm_version_x86.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index 449d669debf..eaf3891905d 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3229,6 +3229,9 @@ VM_Version::VM_Features VM_Version::CpuidInfo::feature_flags() const { } } } + // Unused fields, see the enum definition. + vm_features.set_feature(CPU_MMX_UNUSED); + vm_features.set_feature(CPU_FLUSH_UNUSED); // Composite features. if (supports_tscinv_bit() && From 7a7e742e19f99f251d02130eb5823bf9e9f0fa34 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Sat, 18 Jul 2026 15:59:35 +0200 Subject: [PATCH 43/44] Update CPUFeatures_mandatory comments --- src/hotspot/cpu/x86/vm_version_x86.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index eaf3891905d..a0ecf3441bd 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3423,10 +3423,10 @@ bool VM_Version::is_intrinsic_supported(vmIntrinsicID id) { VM_Features VM_Version::CPUFeatures_mandatory() { VM_Features vm_features; - // SSE and SSE2 are set unconditionally in feature_flags(). + // JDK-8383881 in jdk28+ removed supports_sse(), supports_sse2(), supports_mmx() and supports_clflush(). + // JDK-8383881 has kept the CPU_SSE and CPU_SSE2 bits for an unknown reason. vm_features.set_feature(CPU_SSE); vm_features.set_feature(CPU_SSE2); - // It is for compatibility of the set with older JDKs. vm_features.set_feature(CPU_MMX_UNUSED); vm_features.set_feature(CPU_FLUSH_UNUSED); return vm_features; @@ -3438,7 +3438,7 @@ VM_Features VM_Version::CPUFeatures_generic() { #else VM_Features retval = CPUFeatures_mandatory(); #ifdef AMD64 - // The following options are all in /proc/cpuinfo of one of the first 64-bit CPUs - Atom D2700 (and Opteron 1352): https://superuser.com/q/1572306/1015048 + // The following options are all in /proc/cpuinfo of one of the first 64-bit CPUs - Atom D2700 (and Opteron 1352): https://superuser.com/q/1572306/1015048 retval.set_feature(CPU_FXSR); // enabled in 'gcc -Q --help=target', not used by OpenJDK retval.set_feature(CPU_TSC); // not used by gcc, used by OpenJDK retval.set_feature(CPU_CX8); // gcc detects it to set cpu "pentium" (=32-bit only), used by OpenJDK From 10f923397dbe11df7f92262bc218a65b3c0d53f7 Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Mon, 20 Jul 2026 08:57:47 +0200 Subject: [PATCH 44/44] Update SSE+SSE2 comment --- src/hotspot/cpu/x86/vm_version_x86.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp index a0ecf3441bd..7f0f9346554 100644 --- a/src/hotspot/cpu/x86/vm_version_x86.cpp +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp @@ -3424,7 +3424,7 @@ bool VM_Version::is_intrinsic_supported(vmIntrinsicID id) { VM_Features VM_Version::CPUFeatures_mandatory() { VM_Features vm_features; // JDK-8383881 in jdk28+ removed supports_sse(), supports_sse2(), supports_mmx() and supports_clflush(). - // JDK-8383881 has kept the CPU_SSE and CPU_SSE2 bits for an unknown reason. + // JDK-8384869 has kept CPU_SSE and CPU_SSE2 bits but they are no longer being checked in JDK code. vm_features.set_feature(CPU_SSE); vm_features.set_feature(CPU_SSE2); vm_features.set_feature(CPU_MMX_UNUSED);