Skip to content

Commit 2881af5

Browse files
authored
Merge pull request #12 from opensolvers/site-updates
Update homepage and HPL results
2 parents 2dc4946 + 48d8307 commit 2881af5

5 files changed

Lines changed: 52 additions & 20 deletions

File tree

README.md

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,15 @@
1-
Helping you focus on results instead of compiling and maintaining. OpenSolvers provides a simple service to get your simulations computed.
1+
OpenSolvers explores how open-source scientific software runs on real hardware — starting with **RISC-V** boards and the tools that make that practical (EESSI, OpenBLAS, HPL, and friends). This site documents what we learn along the way.
22

3-
Currently working on several generations of RISC-V cores and validating synthetic performance and real-world applications.
3+
## What we're working on
44

5-
Learnings from different boards:
6-
- [StarFive VisionFive2](boards/VisionFive2.html)
7-
- [OrangePi RV2](boards/RV2.html)
8-
- [BananaPi F3](boards/F3.html)
5+
We're benchmarking **High Performance Linpack (HPL)** across several consumer RISC-V boards, comparing stock and architecture-tuned builds through the [EESSI](https://www.eessi.io/) stack. On the VisionFive 2, a SiFive U74-tuned OpenBLAS lifts HPL from **3.13** to **5.28 GFLOP/s** (**1.69×**) — end-to-end via EESSI and EasyBuild.
96

7+
See the [HPL results overview](boards/hpl.html) for a cross-board summary.
8+
9+
## Boards
10+
11+
- **[StarFive VisionFive 2](boards/VisionFive2.html)** — JH7110 SoC, 4× SiFive U74 (`rv64gc`). EESSI HPL **3.13 → 5.28 GFLOP/s** with U74 OpenBLAS tuning.
12+
- **[OrangePi RV2](boards/RV2.html)** — Ky X1 SoC, 8× SpacemiT X60. Native-arch HPL **7.38 GFLOP/s** (EESSI: DNF, RVV bug in OpenBLAS 0.3.30).
13+
- **[BananaPi F3](boards/F3.html)** — SpacemiT K1 SoC, 8× SpacemiT X60. HPL benchmarking in progress (EESSI: DNF, RVV bug in OpenBLAS 0.3.30).
14+
15+
Use the menu above to jump straight to a board page.

boards/F3.md

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,11 @@
1-
The BananaPi F3 uses the SpaceMit K1 SOC with SpaceMit x60 cores.
1+
The BananaPi F3 uses the SpacemiT K1 SoC with 8× SpacemiT X60 cores.
2+
23
![](f3.jpg)
4+
5+
## HPL
6+
7+
| | Before | After |
8+
| --- | ------ | ----- |
9+
| HPL | DNF ||
10+
11+
Benchmarking in progress. **Before** (EESSI) DNF due to an RVV bug in OpenBLAS 0.3.30. See the [cross-board HPL overview](hpl.html).

boards/RV2.md

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,11 @@
1-
The OrangePi RV2 uses the Ky X1 SOC with SpaceMit x60 cores.
1+
The OrangePi RV2 uses the Ky X1 SoC with 8× SpacemiT X60 cores.
2+
23
![](rv2.png)
34

5+
## HPL
6+
7+
| | Before | After |
8+
| --- | ------ | ----- |
9+
| HPL | DNF | **7.38 GFLOP/s** |
10+
11+
See the [cross-board HPL overview](hpl.html) for full comparison. **Before** (EESSI) DNF due to an RVV bug in OpenBLAS 0.3.30.

boards/VisionFive2.md

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,15 @@ The StarFive VisionFive 2 board is built around the StarFive **JH7110** SoC: fou
44

55
## HPL via EESSI
66

7-
End-to-end benchmark on real VisionFive 2 hardware using [EESSI](https://www.eessi.io/) `2025.06-001` on the RISC-V dev stack [`dev.eessi.io/riscv`](https://www.eessi.io/docs/repositories/dev.eessi.io-riscv/):
7+
See also the [cross-board HPL overview](hpl.html).
88

9-
| Configuration | HPL (N=10000, 4 cores, 2×2 grid) | Speedup |
10-
|---------------|----------------------------------|---------|
11-
| Stock OpenBLAS 0.3.30 (generic `rv64gc` kernel) | **3.13 GFLOP/s** (213 s) | 1.00× |
12-
| U74-optimized OpenBLAS ([easyconfigs#26436](https://github.com/easybuilders/easybuild-easyconfigs/pull/26436)) | **5.28 GFLOP/s** (126 s) | **1.69×** |
9+
End-to-end benchmark on real VisionFive 2 hardware using [EESSI](https://www.eessi.io/) `2025.06-001` on the RISC-V dev stack [`dev.eessi.io/riscv`](https://www.eessi.io/docs/repositories/dev.eessi.io-riscv/). Problem size **N=10000**, block size **NB=192**, **2×2** process grid (4 MPI ranks).
10+
11+
| | Before | After | Speedup |
12+
| --- | ------ | ----- | ------- |
13+
| HPL (N=10000, 4 cores, 2×2 grid) | **3.13 GFLOP/s** (213 s) | **5.28 GFLOP/s** (126 s) | **1.69×** |
14+
15+
**Before** — stock OpenBLAS 0.3.30 (generic `rv64gc` kernel). **After** — U74-optimized OpenBLAS ([easyconfigs#26436](https://github.com/easybuilders/easybuild-easyconfigs/pull/26436)).
1316

1417
Stock OpenBLAS falls back to the generic `RISCV64_GENERIC` C `2×2` GEMM kernel (~3 GFLOP/s on HPL). A hand-tuned scalar **4×4 DGEMM micro-kernel** for the U74 pipeline ([OpenBLAS#5903](https://github.com/OpenMathLib/OpenBLAS/pull/5903)) lifts single-core DGEMM from ~1.4 to **1.77 GFLOP/s** and 4-core DGEMM to **6.31 GFLOP/s**.
1518

boards/hpl.md

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,15 @@
1-
Overview of result of HPL runs, based on march targets on each of the boards.
1+
# HPL results overview
22

3-
Toolchain: GCC 14.3.0, OpenBLAS 0.3.30 and HPL 2.3.0
3+
Cross-board summary of **High Performance Linpack (HPL)** runs on consumer RISC-V hardware, comparing `-march` targets and EESSI stack builds.
44

5-
| board | EESSI (rv64gc) | native arch | rv64imafd |
6-
| ----- | -------------- | ----------- | --------- |
7-
| SF VF2 (4x u74) | 3.28 Gf | | |
8-
| OPi RV2 (8x x60) | DNF | 7.38Gf | 7.34 Gf |
9-
| BPi F3 (8x x60) | DNF | | |
5+
**Toolchain:** GCC 14.3.0, OpenBLAS 0.3.30, HPL 2.3.0. EESSI runs use `2025.06-001` on [`dev.eessi.io/riscv`](https://www.eessi.io/docs/repositories/dev.eessi.io-riscv/).
6+
7+
| Board | Cores | Before | After |
8+
| ----- | ----- | ------ | ----- |
9+
| [StarFive VisionFive 2](VisionFive2.html) | 4× SiFive U74 | 3.13 GFLOP/s | **5.28 GFLOP/s** |
10+
| [OrangePi RV2](RV2.html) | 8× SpacemiT X60 | DNF | 7.38 GFLOP/s |
11+
| [BananaPi F3](F3.html) | 8× SpacemiT X60 | DNF ||
12+
13+
**DNF** — did not finish on the EESSI RISC-V stack, due to an RVV bug in OpenBLAS 0.3.30.
14+
15+
The VisionFive 2 **After** result uses a SiFive U74 OpenBLAS micro-kernel built via EasyBuild, swapped in at runtime with FlexiBLAS — **1.69×** faster than the stock EESSI **Before** build on the same hardware. See the [VisionFive 2 page](VisionFive2.html) and [EESSI/docs#818](https://github.com/EESSI/docs/pull/818) for the full walkthrough.

0 commit comments

Comments
 (0)