You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Copy file name to clipboardExpand all lines: README.md
+2-2Lines changed: 2 additions & 2 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -4,12 +4,12 @@ OpenSolvers explores how open-source scientific software runs on real hardware
4
4
5
5
We're benchmarking **High Performance Linpack (HPL)** across several consumer RISC-V boards, comparing stock and architecture-tuned builds through the [EESSI](https://www.eessi.io/) stack. On the VisionFive 2, a SiFive U74-tuned OpenBLAS lifts HPL from **3.13** to **5.28 GFLOP/s** (**1.69×**) — end-to-end via EESSI and EasyBuild.
6
6
7
-
See the [HPL results overview](boards/hpl.html) for a cross-board summary.
7
+
See the [HPL results overview](apps/hpl.html) for a cross-board summary.
Copy file name to clipboardExpand all lines: boards/RV2.md
+1-1Lines changed: 1 addition & 1 deletion
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -4,7 +4,7 @@ The Orange Pi RV2 is built on the SpaceMiT **K1** SoC: eight **SpacemiT X60** co
4
4
5
5
## HPL via EESSI
6
6
7
-
See also the [cross-board HPL overview](hpl.html).
7
+
See also the [HPL app overview](../apps/hpl.html).
8
8
9
9
Unlike the scalar VisionFive 2, the X60 already dispatches OpenBLAS's upstream **RVV**`RISCV64_ZVL256B` kernels from the stock EESSI stack — but OpenBLAS **0.3.30** has a bug in `gemv_n` that zeroes an uninitialized vector register, so stock EESSI **HPL fails with residual `nan`** (it can still report a plausible ~8.5 GFLOP/s; only the residual check reveals the answer is wrong).
Copy file name to clipboardExpand all lines: boards/VisionFive2.md
+1-1Lines changed: 1 addition & 1 deletion
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -4,7 +4,7 @@ The StarFive VisionFive 2 board is built around the StarFive **JH7110** SoC: fou
4
4
5
5
## HPL via EESSI
6
6
7
-
See also the [cross-board HPL overview](hpl.html).
7
+
See also the [HPL app overview](../apps/hpl.html).
8
8
9
9
End-to-end benchmark on real VisionFive 2 hardware using [EESSI](https://www.eessi.io/)`2025.06-001` on the RISC-V dev stack [`dev.eessi.io/riscv`](https://www.eessi.io/docs/repositories/dev.eessi.io-riscv/). Problem size **N=10000**, block size **NB=192**, **2×2** process grid (4 MPI ranks).
0 commit comments