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Merge pull request #8 from opensolvers/site-updates
Update VisionFive 2 with HPL results from EESSI/docs#818
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_includes/header.html

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<header class="page-header" role="banner">
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<h1 class="project-name">OpenSolvers</h1>
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<h2 class="project-tagline">Running open solvers on RISC-V</h2>
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<h2 class="project-tagline">RISC-V learnings and fun</h2>
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<a href="https://github.com/opensolvers/opensolvers.github.io" class="btn">Find us on GitHub</a>
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boards/VisionFive2.md

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The StarFive VisionFive2 board is build around the StarFive JU7110 SOC.
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The StarFive VisionFive 2 board is built around the StarFive **JH7110** SoC: four **SiFive U74** cores at 1.5 GHz (`rv64gc`, scalar — no vector extension), 8 GB RAM, typically running Ubuntu 24.04.
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![](vf2.jpg)
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## HPL via EESSI
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End-to-end benchmark on real VisionFive 2 hardware using [EESSI](https://www.eessi.io/) `2025.06-001` on the RISC-V dev stack [`dev.eessi.io/riscv`](https://www.eessi.io/docs/repositories/dev.eessi.io-riscv/):
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| Configuration | HPL (N=10000, 4 cores, 2×2 grid) | Speedup |
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|---------------|----------------------------------|---------|
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| Stock OpenBLAS 0.3.30 (generic `rv64gc` kernel) | **3.13 GFLOP/s** (213 s) | 1.00× |
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| U74-optimized OpenBLAS ([easyconfigs#26436](https://github.com/easybuilders/easybuild-easyconfigs/pull/26436)) | **5.28 GFLOP/s** (126 s) | **1.69×** |
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Stock OpenBLAS falls back to the generic `RISCV64_GENERIC` C `2×2` GEMM kernel (~3 GFLOP/s on HPL). A hand-tuned scalar **4×4 DGEMM micro-kernel** for the U74 pipeline ([OpenBLAS#5903](https://github.com/OpenMathLib/OpenBLAS/pull/5903)) lifts single-core DGEMM from ~1.4 to **1.77 GFLOP/s** and 4-core DGEMM to **6.31 GFLOP/s**.
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### Reproducing the optimized run
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1. Set up CVMFS + EESSI on `riscv64` (`EESSI_VERSION_OVERRIDE=2025.06-001`).
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2. Baseline: `module load HPL/2.3-foss-2025b``OMP_NUM_THREADS=1 mpirun -np 4 xhpl`.
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3. Build tuned OpenBLAS from the easyconfig PR: `eb --from-pr 26436 --robot` (via `EESSI-extend` user install).
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4. Register the new backend with FlexiBLAS and re-run the same `xhpl` — no HPL rebuild.
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Full walkthrough: [EESSI/docs#818](https://github.com/EESSI/docs/pull/818)*A 1.7× faster HPL on a RISC-V SiFive U74 via EESSI*.

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