GDP plugin support patches#11626
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Add two opt-in fields to uct_ib_mlx5_qp_attr_t for QPs whose send doorbell is rung from a DPA thread: - sq_no_dbr: create the QP with qpc.send_dbr_mode = NO_DBR_INT and register no send doorbell-record umem (skip dbr_addr/dbr_umem_id), so the NIC does not read the SQ dbr. Required when the dbr lives in DPA memory the NIC cannot read; the producer rings the DB register only. Assumes no RQ. - uar_page_id: override the QPC uar_page (0 = worker UAR). The DPA thread rings via flexio_dev_qp_sq_ring_db() through its outbox, which maps the FlexIO process UAR, so the QP's uar_page must match that UAR (not the host worker's) for the doorbell to drive the QP. Both default off, so existing QPs are unchanged. Adds the send_dbr_mode qpc field/enum to the IFC header (carved out of reserved_at_80, layout preserved). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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rakhmets
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| @@ -1,28 +1,6 @@ | |||
| # | |||
| # Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2017. ALL RIGHTS RESERVED. | |||
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| # Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2017. ALL RIGHTS RESERVED. | |
| # Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2026. ALL RIGHTS RESERVED. |
| UCT_IB_MLX5_QPC_SQ_DBR_VALID = 0x0, | ||
| UCT_IB_MLX5_QPC_SQ_NO_DBR_EXT = 0x1, | ||
| UCT_IB_MLX5_QPC_SQ_NO_DBR_INT = 0x2 | ||
| }; |
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| template<ucs_device_level_t level> | ||
| UCS_F_DEVICE void uct_dev_exec_init(unsigned &lane_id, unsigned &num_lanes) |
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please consider returning struct with two fields instead.
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this may prevent registers use
| uct_dev_exec_init<level>(lane_id, num_lanes); | ||
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| if (lane_id == 0) { | ||
| long long depth = UCS_BIT(ep->log_depth); |
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| for (;;) { | ||
| unsigned long long ci = READ_ONCE(*ep->ci); | ||
| if ((long long)(pi - ci) >= depth) { |
| } | ||
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| if (status == UCS_INPROGRESS) { | ||
| uint32_t slot = pi & UCS_MASK(ep->log_depth); |
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| status = (ucs_status_t)uct_dev_bcast<level>((int)status, lane_id); | ||
| return status; |
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| status = (ucs_status_t)uct_dev_bcast<level>((int)status, lane_id); | |
| return status; | |
| return static_cast<ucs_status_t>(uct_dev_bcast<level>(static_cast<int>(status), | |
| lane_id)); |
| src_ib->lkey, | ||
| reinterpret_cast<uint64_t>(address), | ||
| rem_ib->rkey, remote_address, 0, | ||
| comp == NULL ? 0 : |
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| comp == NULL ? 0 : | |
| comp == nullptr ? 0 : |
| sizeof(uint64_t), ep->atomic_result_lkey, | ||
| ep->atomic_result_va, rem_ib->rkey, | ||
| remote_address, inc_value, | ||
| comp == NULL ? 0 : |
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| comp == NULL ? 0 : | |
| comp == nullptr ? 0 : |
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| UCT_IB_D2P_OP_RDMA_WRITE = 0, | ||
| UCT_IB_D2P_OP_ATOMIC_ADD = 1, |
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Why do we need these operation codes? I see the opcode is set, but where should we check it?
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It's common protocol which may be used by different proxies.
example https://gitlab-master.nvidia.com/nbu-swx/ai/ucx-spcx-plugin/-/merge_requests/22/diffs#a0011c5941e2b14f2a81fcba6dd8347c939c88e6_0_169
rakhmets
previously approved these changes
Jul 9, 2026
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