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2 changes: 1 addition & 1 deletion config/cuda.am
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ NVCC_CMD = $(NVCC_WRAP) $(NVCC) -DHAVE_CONFIG_H \
NVCC_LT_CMD = $(LIBTOOL) --tag=CXX --mode=compile $(NVCC_CMD)

define nvcc-build
@$(MKDIR_P) $(shell dirname $(DEPDIR)/cuda/$@)
@$(MKDIR_P) $(@D) $(shell dirname $(DEPDIR)/cuda/$@)
@$(if $(filter false,$(AM_V_P)),echo " NVCC $@")
@$(if $(filter .o,$(suffix $@)),$(NVCC_CMD),$(NVCC_LT_CMD)) $($(1)) $(if $(filter false,$(AM_V_P)), >/dev/null)
endef
Expand Down
45 changes: 22 additions & 23 deletions config/m4/cuda.m4
Original file line number Diff line number Diff line change
@@ -1,28 +1,6 @@
#
# Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2017. ALL RIGHTS RESERVED.
# Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2026. ALL RIGHTS RESERVED.
# See file LICENSE for terms.
#

NVCC_CUDA_MIN_REQUIRED=12.2

ARCH9_CODE="-gencode=arch=compute_70,code=sm_70"
ARCH10_CODE="-gencode=arch=compute_75,code=sm_75"
ARCH110_CODE="-gencode=arch=compute_80,code=sm_80"
ARCH111_CODE="-gencode=arch=compute_86,code=sm_86"
ARCH120_CODE="-gencode=arch=compute_90,code=sm_90"
ARCH124_CODE="-gencode=arch=compute_89,code=sm_89"
ARCH128_CODE="-gencode=arch=compute_100,code=sm_100 -gencode=arch=compute_120,code=sm_120"
ARCH130_CODE="-gencode=arch=compute_110,code=sm_110"


ARCH9_PTX="-gencode=arch=compute_70,code=compute_70"
ARCH10_PTX=""
ARCH110_PTX="-gencode=arch=compute_80,code=compute_80"
ARCH111_PTX="-gencode=arch=compute_86,code=compute_86"
ARCH120_PTX="-gencode=arch=compute_90,code=compute_90"
ARCH124_PTX="-gencode=arch=compute_90,code=compute_90"
ARCH128_PTX="-gencode=arch=compute_120,code=compute_120"
ARCH130_PTX="-gencode=arch=compute_120,code=compute_120"

# Define CUDA language
AC_LANG_DEFINE([CUDA], [cuda], [NVCC], [NVCC], [C++], [
Expand All @@ -46,6 +24,27 @@ AC_DEFUN([AC_LANG_COMPILER(CUDA)], [

# Check for nvcc compiler support
AC_DEFUN([UCX_CUDA_CHECK_NVCC], [
NVCC_CUDA_MIN_REQUIRED=12.2

ARCH9_CODE="-gencode=arch=compute_70,code=sm_70"
ARCH10_CODE="-gencode=arch=compute_75,code=sm_75"
ARCH110_CODE="-gencode=arch=compute_80,code=sm_80"
ARCH111_CODE="-gencode=arch=compute_86,code=sm_86"
ARCH120_CODE="-gencode=arch=compute_90,code=sm_90"
ARCH124_CODE="-gencode=arch=compute_89,code=sm_89"
ARCH128_CODE="-gencode=arch=compute_100,code=sm_100 -gencode=arch=compute_120,code=sm_120"
ARCH130_CODE="-gencode=arch=compute_110,code=sm_110"


ARCH9_PTX="-gencode=arch=compute_70,code=compute_70"
ARCH10_PTX=""
ARCH110_PTX="-gencode=arch=compute_80,code=compute_80"
ARCH111_PTX="-gencode=arch=compute_86,code=compute_86"
ARCH120_PTX="-gencode=arch=compute_90,code=compute_90"
ARCH124_PTX="-gencode=arch=compute_90,code=compute_90"
ARCH128_PTX="-gencode=arch=compute_120,code=compute_120"
ARCH130_PTX="-gencode=arch=compute_120,code=compute_120"

AS_IF([test "x$NVCC" != "x"], [
CUDA_VERSION=$($NVCC --version | grep release | sed 's/.*release //' | sed 's/\,.*//')
CUDA_MAJOR_VERSION=$(echo $CUDA_VERSION | cut -d "." -f 1)
Expand Down
25 changes: 25 additions & 0 deletions src/uct/api/device/uct_device_impl.h
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,14 @@
#define UCT_RC_MLX5_GDA_SUPPORTED 0
#endif

#if __has_include(<uct/ib/mlx5/gdaki/d2p.cuh>) && \
__has_include(<infiniband/mlx5dv.h>)
#include <uct/ib/mlx5/gdaki/d2p.cuh>
#define UCT_D2P_SUPPORTED 1
#else
#define UCT_D2P_SUPPORTED 0
#endif

union uct_device_completion {
#if UCT_RC_MLX5_GDA_SUPPORTED
uct_rc_gda_completion_t rc_gda;
Expand Down Expand Up @@ -88,6 +96,12 @@ UCS_F_DEVICE ucs_status_t uct_device_ep_put(
remote_address, length, flags, comp);
}
#endif
#if UCT_D2P_SUPPORTED
if (device_ep->uct_tl_id == UCT_DEVICE_TL_D2P) {
return uct_ib_d2p_ep_put<level>(device_ep, src_uct_elem, mem_elem, address,
remote_address, length, flags, comp);
}
#endif

return UCS_ERR_UNSUPPORTED;
}
Expand Down Expand Up @@ -139,6 +153,12 @@ UCS_F_DEVICE ucs_status_t uct_device_ep_atomic_add(
remote_address, flags, comp);
}
#endif
#if UCT_D2P_SUPPORTED
if (device_ep->uct_tl_id == UCT_DEVICE_TL_D2P) {
return uct_ib_d2p_ep_atomic_add<level>(device_ep, mem_elem, inc_value,
remote_address, flags, comp);
}
#endif

return UCS_ERR_UNSUPPORTED;
}
Expand Down Expand Up @@ -210,6 +230,11 @@ UCS_F_DEVICE ucs_status_t uct_device_ep_check_completion(
return uct_rc_mlx5_gda_ep_check_completion<level>(device_ep, comp);
}
#endif
#if UCT_D2P_SUPPORTED
if (device_ep->uct_tl_id == UCT_DEVICE_TL_D2P) {
return uct_ib_d2p_ep_check_completion<level>(device_ep, comp);
}
#endif

return UCS_ERR_UNSUPPORTED;
}
Expand Down
1 change: 1 addition & 0 deletions src/uct/api/device/uct_device_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,7 @@ typedef enum {
typedef enum {
UCT_DEVICE_TL_RC_MLX5_GDA,
UCT_DEVICE_TL_CUDA_IPC,
UCT_DEVICE_TL_D2P,
UCT_DEVICE_TL_LAST
} uct_device_tl_id_t;

Expand Down
14 changes: 11 additions & 3 deletions src/uct/ib/mlx5/dv/ib_mlx5_dv.c
Original file line number Diff line number Diff line change
Expand Up @@ -183,7 +183,8 @@ ucs_status_t uct_ib_mlx5_devx_create_qp_common(uct_ib_iface_t *iface,
UCT_IB_MLX5DV_SET(qpc, qpc, pm_state, UCT_IB_MLX5_QPC_PM_STATE_MIGRATED);
UCT_IB_MLX5DV_SET(qpc, qpc, rdma_wr_disabled, !!attr->rdma_wr_disabled);
UCT_IB_MLX5DV_SET(qpc, qpc, pd, uct_ib_mlx5_devx_md_get_pdn(md));
UCT_IB_MLX5DV_SET(qpc, qpc, uar_page, uar->uar->page_id);
UCT_IB_MLX5DV_SET(qpc, qpc, uar_page,
attr->uar_page_id ? attr->uar_page_id : uar->uar->page_id);
ucs_assert((attr->super.srq == NULL) || (attr->super.srq_num != 0));
UCT_IB_MLX5DV_SET(qpc, qpc, rq_type, attr->super.srq_num ? 1 /* SRQ */ :
3 /* no RQ */);
Expand All @@ -197,8 +198,15 @@ ucs_status_t uct_ib_mlx5_devx_create_qp_common(uct_ib_iface_t *iface,
uct_ib_mlx5_qpc_cs_req(attr->super.max_inl_cqe[UCT_IB_DIR_TX]));
UCT_IB_MLX5DV_SET(qpc, qpc, cs_res,
uct_ib_mlx5_qpc_cs_res(attr->super.max_inl_cqe[UCT_IB_DIR_RX], 0));
UCT_IB_MLX5DV_SET64(qpc, qpc, dbr_addr, qp->devx.dbrec->offset);
UCT_IB_MLX5DV_SET(qpc, qpc, dbr_umem_id, qp->devx.dbrec->mem_id);
if (attr->sq_no_dbr) {
UCT_IB_MLX5DV_SET(qpc, qpc, send_dbr_mode,
UCT_IB_MLX5_QPC_SQ_NO_DBR_INT);
} else {
UCT_IB_MLX5DV_SET(qpc, qpc, send_dbr_mode,
UCT_IB_MLX5_QPC_SQ_DBR_VALID);
UCT_IB_MLX5DV_SET64(qpc, qpc, dbr_addr, qp->devx.dbrec->offset);
UCT_IB_MLX5DV_SET(qpc, qpc, dbr_umem_id, qp->devx.dbrec->mem_id);
}
UCT_IB_MLX5DV_SET(qpc, qpc, user_index, attr->uidx);
UCT_IB_MLX5DV_SET(qpc, qpc, ts_format, UCT_IB_MLX5_QPC_TS_FORMAT_DEFAULT);

Expand Down
8 changes: 7 additions & 1 deletion src/uct/ib/mlx5/dv/ib_mlx5_ifc.h
Original file line number Diff line number Diff line change
Expand Up @@ -1377,6 +1377,11 @@ enum {
UCT_IB_MLX5_QPC_TS_FORMAT_REAL_TIME = 0x2
};

enum {
UCT_IB_MLX5_QPC_SQ_DBR_VALID = 0x0,
UCT_IB_MLX5_QPC_SQ_NO_DBR_INT = 0x2
};

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unused?


struct uct_ib_mlx5_qpc_bits {
uint8_t state[0x4];
uint8_t lag_tx_port_affinity[0x4];
Expand Down Expand Up @@ -1415,7 +1420,8 @@ struct uct_ib_mlx5_qpc_bits {
uint8_t counter_set_id[0x8];
uint8_t uar_page[0x18];

uint8_t reserved_at_80[0x3];
uint8_t send_dbr_mode[0x2];
uint8_t reserved_at_82[0x1];
uint8_t full_handshake[0x1];
uint8_t cnak_reverse_sl[0x4];
uint8_t user_index[0x18];
Expand Down
4 changes: 4 additions & 0 deletions src/uct/ib/mlx5/gdaki/Makefile.am
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,10 @@ libuct_ib_mlx5_gda_la_SOURCES = \
nobase_dist_libuct_ib_mlx5_gda_la_HEADERS = \
gdaki.cuh \
gdaki_dev.h \
common.cuh \
d2p.cuh \
d2p.h \
d2p_proto.h \
gpunetio/common/doca_gpunetio_verbs_def.h \
gpunetio/common/doca_gpunetio_verbs_dev.h \
gpunetio/device/doca_gpunetio_dev_verbs_common.cuh \
Expand Down
81 changes: 81 additions & 0 deletions src/uct/ib/mlx5/gdaki/common.cuh
Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@
/**
* Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2026. ALL RIGHTS RESERVED.
*
* See file LICENSE for terms.
*/

#ifndef UCT_DEV_COMMON_CUH_
#define UCT_DEV_COMMON_CUH_

#include <ucs/sys/device_code.h>

#include <infiniband/mlx5dv.h> /* TODO add to gpunetio */
#include <cuda.h> /* TODO add to gpunetio */
#include "gpunetio/device/doca_gpunetio_dev_verbs_common.cuh"
#include <cooperative_groups.h>


template<ucs_device_level_t level>
UCS_F_DEVICE void uct_dev_exec_init(unsigned &lane_id, unsigned &num_lanes)
Comment thread
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{
switch (level) {
case UCS_DEVICE_LEVEL_THREAD:
lane_id = 0;
num_lanes = 1;
break;
case UCS_DEVICE_LEVEL_WARP:
lane_id = doca_gpu_dev_verbs_get_lane_id();
num_lanes = UCS_DEVICE_NUM_THREADS_IN_WARP;
break;
case UCS_DEVICE_LEVEL_BLOCK:
lane_id = threadIdx.x;
num_lanes = blockDim.x;
break;
case UCS_DEVICE_LEVEL_GRID:
lane_id = threadIdx.x + blockIdx.x * blockDim.x;
num_lanes = blockDim.x * gridDim.x;
break;
}
}

template<ucs_device_level_t level> UCS_F_DEVICE void uct_dev_sync(void)
{
switch (level) {
case UCS_DEVICE_LEVEL_WARP:
__syncwarp();
break;
case UCS_DEVICE_LEVEL_BLOCK:
__syncthreads();
break;
case UCS_DEVICE_LEVEL_THREAD:
break;
case UCS_DEVICE_LEVEL_GRID:
auto g = cooperative_groups::this_grid();
g.sync();
}
}

template<ucs_device_level_t level>
UCS_F_DEVICE int uct_dev_bcast(int value, unsigned lane_id)
{
switch (level) {
case UCS_DEVICE_LEVEL_WARP:
return __shfl_sync(0xffffffff, value, 0);
case UCS_DEVICE_LEVEL_BLOCK: {
__shared__ int shared_value;
if (lane_id == 0) {
shared_value = value;
}
__syncthreads();
value = shared_value;
__syncthreads();
return value;
}
case UCS_DEVICE_LEVEL_THREAD:
case UCS_DEVICE_LEVEL_GRID:
default:
return value;
}
}

#endif /* UCT_DEV_COMMON_CUH_ */
116 changes: 116 additions & 0 deletions src/uct/ib/mlx5/gdaki/d2p.cuh
Original file line number Diff line number Diff line change
@@ -0,0 +1,116 @@
/**
* Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2026. ALL RIGHTS RESERVED.
*
* See file LICENSE for terms.
*/

#ifndef UCT_D2P_CUH_
#define UCT_D2P_CUH_

#include "d2p.h"
#include "d2p_proto.h"
#include "common.cuh"

#include <uct/api/device/uct_device_types.h>
#include <ucs/sys/device_code.h>


template<ucs_device_level_t level>
UCS_F_DEVICE ucs_status_t uct_ib_d2p_post_desc(uct_ib_d2p_gpu_ep_t *ep,
uint8_t opcode, uint32_t length,
uint32_t lkey, uint64_t laddr,
uint32_t rkey, uint64_t raddr,
uint64_t add, uint16_t flags)
{
ucs_status_t status = UCS_INPROGRESS;
unsigned lane_id, num_lanes;

uct_dev_exec_init<level>(lane_id, num_lanes);

if (lane_id == 0) {
const long long depth = UCS_BIT(ep->log_depth);
unsigned long long pi = READ_ONCE(*ep->pi);

for (;;) {
unsigned long long ci = READ_ONCE(*ep->ci);
if (static_cast<long long>(pi - ci) >= depth) {
status = UCS_ERR_NO_RESOURCE;
break;
}

unsigned long long prev = atomicCAS(ep->pi, pi, pi + 1);
if (prev == pi) {
break;
}
pi = prev;
}

if (status == UCS_INPROGRESS) {
const uint32_t slot = pi & UCS_MASK(ep->log_depth);
auto desc = reinterpret_cast<volatile uct_ib_d2p_desc_t*>(
ep->queue_base) +
slot;

desc->opcode = opcode;
desc->length = length;
desc->qp_idx = ep->qp_idx;
desc->lkey = lkey;
desc->laddr = laddr;
desc->rkey = rkey;
desc->raddr = raddr;
desc->add = add;
desc->flags = flags;
desc->owner = (pi >> ep->log_depth) & 0x1;

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Is a __threadfence(); missing here?

}
}

return static_cast<ucs_status_t>(
uct_dev_bcast<level>(static_cast<int>(status), lane_id));
}

template<ucs_device_level_t level>
UCS_F_DEVICE ucs_status_t uct_ib_d2p_ep_put(
uct_device_ep_h tl_ep, const uct_device_mem_elem_t *src_uct_elem,
const uct_device_mem_elem_t *tl_mem_elem, const void *address,
uint64_t remote_address, size_t length, uint64_t flags,
uct_device_completion_t *comp)
{
auto ep = reinterpret_cast<uct_ib_d2p_gpu_ep_t*>(tl_ep);
auto src_ib = reinterpret_cast<const uct_ib_md_device_mem_element_t*>(
src_uct_elem);
auto rem_ib = reinterpret_cast<const uct_ib_md_device_mem_element_t*>(
tl_mem_elem);

return uct_ib_d2p_post_desc<level>(
ep, UCT_IB_D2P_OP_RDMA_WRITE, length, src_ib->lkey,
reinterpret_cast<uint64_t>(address), rem_ib->rkey, remote_address,
0, comp == nullptr ? 0 : UCT_IB_D2P_FLAG_CQ_UPDATE);
}

template<ucs_device_level_t level>
UCS_F_DEVICE ucs_status_t uct_ib_d2p_ep_atomic_add(
uct_device_ep_h tl_ep, const uct_device_mem_elem_t *tl_mem_elem,
uint64_t inc_value, uint64_t remote_address, uint64_t flags,
uct_device_completion_t *comp)
{
auto ep = reinterpret_cast<uct_ib_d2p_gpu_ep_t*>(tl_ep);
auto rem_ib = reinterpret_cast<const uct_ib_md_device_mem_element_t*>(
tl_mem_elem);

return uct_ib_d2p_post_desc<level>(ep, UCT_IB_D2P_OP_ATOMIC_ADD,
sizeof(uint64_t), ep->atomic_result_lkey,
ep->atomic_result_va, rem_ib->rkey,
remote_address, inc_value,
comp == nullptr ?
0 :
UCT_IB_D2P_FLAG_CQ_UPDATE);
}

template<ucs_device_level_t level>
UCS_F_DEVICE ucs_status_t uct_ib_d2p_ep_check_completion(
uct_device_ep_h tl_ep, uct_device_completion_t *comp)
{
return UCS_OK;

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That means it's always completed?

}

#endif /* UCT_D2P_CUH_ */
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