Commit 59dfcdd
[CPU][ARM] Guard ARM SVE kernel entry points (#36453)
## Cause
- On AArch64 with GCC (cross-compile, gcc-10) + LTO,
`-march=armv8-a+sve` target attributes from runtime-dispatched SVE
clones leak into generic ARMv8-A baseline code.
- GCC auto-vectorizes generic helpers (e.g. `std::vector<...>` resize in
the SVE PagedAttention `AttentionExecutor::init`) with SVE instructions
(`mov z0.b, #0` / `whilelo` / `st1d`).
- On cores without SVE (e.g. Cortex-A72) these are illegal instructions
→ SIGILL at runtime (reached on a TBB worker thread).
- `brgemm_kernel.cpp` ISA selection unconditionally fell back to
`sve_128` without checking `mayiuse(...)`, so it built oneDNN kernels
that emit SVE on cores without SVE.
## Solution
- `precision_support`: add a single ARM ISA gate — `enum class ArmISA {
ASIMD, SVE, DOTPROD, I8MM }` and `bool hasArmISASupport(ArmISA)` (ASIMD
→ always true baseline, SVE → `with_cpu_sve()`, DOTPROD/I8MM →
`with_cpu_arm_*`). It consolidates the former
`hasIntDotProductSupport()` / `hasInt8MMSupport()` helpers.
Declared/defined for ARM targets only, so x86_64 / RISC-V are
unaffected.
- ACL executors: encapsulate the precondition common to every ACL
executor in `aclCommonExecutorSupported()` (in `acl_utils.hpp`; today
the ARMv8-A NEON/ASIMD baseline, extensible). Each ACL executor calls it
in its `supports()` / `isSupported()` predicate (`VERIFY(...,
UNSUPPORTED_ACL_COMMON_PRECONDITION)` or `if/return` + `DEBUG_LOG`),
keeping its op-specific checks. ASIMD is always present on AArch64, so
this never over-restricts.
- `kleidiai_mm` / `fullyconnected` (KleidiAI path): query
`hasArmISASupport` directly (ASIMD, plus DOTPROD/I8MM for ukernel
selection).
- `brgemm_kernel.cpp`: `getSupportedSveIsa(min_isa = sve_128)` returns
the highest supported SVE ISA at or above `min_isa`, or `isa_undef`
(then the caller throws) instead of the unconditional `sve_128`
fallback. The main brgemm kernel uses the default `sve_128` floor; the
`copy_a` / `copy_b` kernels pass `sve_256` (oneDNN only provides
`sve_256`/`sve_512` for them — `create_brgemm_matmul_copy_*` asserts a
superset of `sve_256`).
- `paged_attn.cpp`: decline the ARM PagedAttention executor when the
core has no SVE (`hasArmISASupport(ArmISA::SVE)`), in the baseline
caller before `make_pa_executor` dispatches to the SVE clone, so the
SVE-autovectorized `AttentionExecutor::init` is never reached. The node
throws cleanly instead.
- SVE codegen is unchanged: SVE-capable cores keep SVE paths; non-SVE
cores decline them and fall back to ANY/NEON.
## Tickets
- CVS-179098
---------
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>1 parent 45c62b7 commit 59dfcdd
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- acl
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- kernels/aarch64
- utils
- tests/functional
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