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chore: fix lint
1 parent 4887fe6 commit 4b07c41

2 files changed

Lines changed: 3 additions & 5 deletions

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extensions/riscv/circuit/src/adapters/loadstore.rs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,9 +41,8 @@ use openvm_stark_backend::{
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use super::{
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byte_ptr_limbs_to_cell_ptr_limbs_value, cell_ptr_hi_bits,
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eval_byte_ptr_limbs_to_u16_cell_ptr_limbs, expand_to_rv64_block, ptr_to_field_u16_limbs,
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ptr_to_u16_limbs, reg_byte_ptr_to_cell_ptr_limbs, rv64_address_add_imm, sign_extend_imm16, try_rv64_bytes_to_u32, RV64_PTR_BITS,
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RV64_PTR_U16_LIMBS,
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RV64_REGISTER_NUM_LIMBS, U16_BITS,
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ptr_to_u16_limbs, reg_byte_ptr_to_cell_ptr_limbs, rv64_address_add_imm, sign_extend_imm16,
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try_rv64_bytes_to_u32, RV64_PTR_BITS, RV64_PTR_U16_LIMBS, RV64_REGISTER_NUM_LIMBS, U16_BITS,
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};
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use crate::adapters::{memory_read, timed_write, tracing_read};
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extensions/riscv/circuit/src/loadstore/tests.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ use openvm_circuit_primitives::{
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},
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var_range::VariableRangeCheckerChip,
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};
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use openvm_instructions::{instruction::Instruction, riscv::RV64_REGISTER_AS, LocalOpcode};
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use openvm_instructions::{instruction::Instruction, LocalOpcode};
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use openvm_riscv_transpiler::Rv64LoadStoreOpcode::{self, *};
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use openvm_stark_backend::{
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p3_air::BaseAir,
@@ -402,7 +402,6 @@ fn positive_storew_public_values_test() {
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tester.simple_test().expect("Verification failed");
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}
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//////////////////////////////////////////////////////////////////////////////////////
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// NEGATIVE TESTS
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//

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