perf(v2.1): split rv64 load/store by operation and width#2922

Open

shuklaayush wants to merge 26 commits into

develop-v2.1.0-rv64from

codex/int-7671-loadstore-split-rv64

Commits on Jul 9, 2026

perf(riscv): split rv64 loadstore by cell width

shuklaayush
authored and
GunaDD
committed
feat(riscv): add cuda tracegen for split loadstore

shuklaayush
authored and
GunaDD
committed
docs(riscv): split loadstore README sections

shuklaayush
authored and
GunaDD
committed
refactor(riscv): colocate loadstore cuda wrappers

shuklaayush
authored and
GunaDD
committed
refactor(riscv): split loadstore tests by width

shuklaayush
authored and
GunaDD
committed
refactor(riscv): colocate loadstore width tests

shuklaayush
authored and
GunaDD
committed
refactor(riscv): split loadstore cuda kernels

shuklaayush
authored and
GunaDD
committed
refactor(riscv): split loadstore chips by operation

shuklaayush
authored and
GunaDD
committed
fix(riscv): import cuda test traits

shuklaayush
authored and
GunaDD
committed
fix(riscv): order memory test helpers for clippy

shuklaayush
authored and
GunaDD
committed
fix(deps): update quinn-proto audit advisory

shuklaayush
authored and
GunaDD
committed
refactor(riscv): clarify width-aligned memory cores

shuklaayush
authored and
GunaDD
committed
refactor(riscv): split load store cuda kernels

shuklaayush
authored and
GunaDD
committed
refactor(riscv): compact load store trace records

shuklaayush
authored and
GunaDD
committed
refactor(riscv): rename load store width generics

GunaDD
and
claude
committed
refactor(riscv): flatten width-aligned load store modules

GunaDD
and
claude
committed
refactor(riscv): inline load store adapter air contexts

GunaDD
and
claude
committed
refactor(riscv): normalize load store case constant names

GunaDD
and
claude
committed
refactor(riscv): drop redundant load store num cases generic

GunaDD
and
claude
committed
refactor(riscv): rename width aligned load store cores and add chip infos

GunaDD
and
claude
committed
refactor(riscv): import load store adapter fillers at file top

GunaDD
and
claude
committed
refactor(riscv): drop vestigial U8 wrapper in load store execution

GunaDD
and
claude
committed
refactor(riscv): inline load store test helpers and clarify mem_as docs

GunaDD
and
claude
committed
refactor(riscv): remove unused opcode enums from cuda load store headers

GunaDD
and
claude
committed
refactor(riscv): drop _kernel suffix from load store tracegen kernels

GunaDD
and
claude
committed
refactor(riscv): rename alignment to alignment_bit in load sign extend test utils

GunaDD
and
claude
committed

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perf(v2.1): split rv64 load/store by operation and width#2922

perf(v2.1): split rv64 load/store by operation and width#2922
shuklaayush wants to merge 26 commits into
develop-v2.1.0-rv64from
codex/int-7671-loadstore-split-rv64

Commits on Jul 9, 2026

perf(riscv): split rv64 loadstore by cell width

feat(riscv): add cuda tracegen for split loadstore

docs(riscv): split loadstore README sections

refactor(riscv): colocate loadstore cuda wrappers

refactor(riscv): split loadstore tests by width

refactor(riscv): colocate loadstore width tests

refactor(riscv): split loadstore cuda kernels

refactor(riscv): split loadstore chips by operation

fix(riscv): import cuda test traits

fix(riscv): order memory test helpers for clippy

fix(deps): update quinn-proto audit advisory

refactor(riscv): clarify width-aligned memory cores

refactor(riscv): split load store cuda kernels

refactor(riscv): compact load store trace records

refactor(riscv): rename load store width generics

refactor(riscv): flatten width-aligned load store modules

refactor(riscv): inline load store adapter air contexts

refactor(riscv): normalize load store case constant names

refactor(riscv): drop redundant load store num cases generic

refactor(riscv): rename width aligned load store cores and add chip infos

refactor(riscv): import load store adapter fillers at file top

refactor(riscv): drop vestigial U8 wrapper in load store execution

refactor(riscv): inline load store test helpers and clarify mem_as docs

refactor(riscv): remove unused opcode enums from cuda load store headers

refactor(riscv): drop _kernel suffix from load store tracegen kernels

refactor(riscv): rename alignment to alignment_bit in load sign extend test utils