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78bf93f
perf(riscv): split rv64 loadstore by cell width
shuklaayush Jun 21, 2026
3431f19
feat(riscv): add cuda tracegen for split loadstore
shuklaayush Jun 24, 2026
f882fc1
docs(riscv): split loadstore README sections
shuklaayush Jun 24, 2026
4905e42
refactor(riscv): colocate loadstore cuda wrappers
shuklaayush Jun 24, 2026
8b53ac3
refactor(riscv): split loadstore tests by width
shuklaayush Jun 24, 2026
bc69a1e
refactor(riscv): colocate loadstore width tests
shuklaayush Jun 24, 2026
10f476b
refactor(riscv): split loadstore cuda kernels
shuklaayush Jun 24, 2026
e6b9ea5
refactor(riscv): split loadstore chips by operation
shuklaayush Jun 26, 2026
124b81b
fix(riscv): import cuda test traits
shuklaayush Jun 26, 2026
a601dd5
fix(riscv): order memory test helpers for clippy
shuklaayush Jun 26, 2026
0d7e127
fix(deps): update quinn-proto audit advisory
shuklaayush Jun 26, 2026
d8f38b9
refactor(riscv): clarify width-aligned memory cores
shuklaayush Jun 29, 2026
cc6cf29
refactor(riscv): split load store cuda kernels
shuklaayush Jun 29, 2026
ef29d2d
refactor(riscv): compact load store trace records
shuklaayush Jun 29, 2026
b5a660e
refactor(riscv): rename load store width generics
GunaDD Jul 9, 2026
dee47cb
refactor(riscv): flatten width-aligned load store modules
GunaDD Jul 9, 2026
246135e
refactor(riscv): inline load store adapter air contexts
GunaDD Jul 9, 2026
996b171
refactor(riscv): normalize load store case constant names
GunaDD Jul 9, 2026
273bd68
refactor(riscv): drop redundant load store num cases generic
GunaDD Jul 9, 2026
5ae22d8
refactor(riscv): rename width aligned load store cores and add chip i…
GunaDD Jul 9, 2026
aa2f173
refactor(riscv): import load store adapter fillers at file top
GunaDD Jul 9, 2026
a80d6bf
refactor(riscv): drop vestigial U8 wrapper in load store execution
GunaDD Jul 9, 2026
b07fe02
refactor(riscv): inline load store test helpers and clarify mem_as docs
GunaDD Jul 9, 2026
b09e436
refactor(riscv): remove unused opcode enums from cuda load store headers
GunaDD Jul 9, 2026
48112df
refactor(riscv): drop _kernel suffix from load store tracegen kernels
GunaDD Jul 9, 2026
eed6502
refactor(riscv): rename alignment to alignment_bit in load sign exten…
GunaDD Jul 9, 2026
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8 changes: 4 additions & 4 deletions Cargo.lock

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114 changes: 114 additions & 0 deletions extensions/riscv/circuit/cuda/include/riscv/adapters/load.cuh
Original file line number Diff line number Diff line change
@@ -0,0 +1,114 @@
#pragma once

#include "primitives/execution.h"
#include "primitives/trace_access.h"
#include "primitives/utils.cuh"
#include "system/memory/controller.cuh"
#include "system/memory/offline_checker.cuh"

using namespace riscv;

template <typename T> struct Rv64LoadAdapterCols {
ExecutionState<T> from_state;
T rs1_ptr;
T rs1_data[RV64_PTR_U16_LIMBS];
MemoryReadAuxCols<T> rs1_aux_cols;
T rd_ptr;
MemoryReadAuxCols<T> read_data_aux;
T imm;
T imm_sign;
T mem_ptr_limbs[2];
MemoryWriteAuxCols<T, BLOCK_FE_WIDTH> write_aux;
T needs_write;
};

struct Rv64LoadAdapterRecord {
uint32_t from_pc;
uint32_t from_timestamp;

uint32_t rs1_ptr;
uint32_t rs1_val;
MemoryReadAuxRecord rs1_aux_record;

uint32_t rd_ptr;
MemoryReadAuxRecord read_data_aux;
uint16_t imm;
bool imm_sign;

uint32_t write_prev_timestamp;
uint16_t write_prev_data[BLOCK_FE_WIDTH];
};

static __device__ __forceinline__ uint32_t
rv64_load_effective_ptr(Rv64LoadAdapterRecord record) {
return record.rs1_val + uint32_t(record.imm) +
uint32_t(record.imm_sign) * (uint32_t(UINT16_MAX) << U16_BITS);
}

static __device__ __forceinline__ uint32_t rv64_load_shift_amount(Rv64LoadAdapterRecord record) {
return rv64_load_effective_ptr(record) & (RV64_REGISTER_NUM_LIMBS - 1);
}

struct Rv64LoadAdapter {
size_t pointer_max_bits;
VariableRangeChecker range_checker;
MemoryAuxColsFactory mem_helper;

__device__ Rv64LoadAdapter(
size_t pointer_max_bits,
VariableRangeChecker range_checker,
uint32_t timestamp_max_bits
)
: pointer_max_bits(pointer_max_bits), range_checker(range_checker),
mem_helper(range_checker, timestamp_max_bits) {}

__device__ void fill_trace_row(RowSlice row, Rv64LoadAdapterRecord record) {
COL_WRITE_VALUE(row, Rv64LoadAdapterCols, from_state.pc, record.from_pc);
COL_WRITE_VALUE(row, Rv64LoadAdapterCols, from_state.timestamp, record.from_timestamp);
COL_WRITE_VALUE(row, Rv64LoadAdapterCols, rs1_ptr, record.rs1_ptr);

Fp rs1_data[RV64_PTR_U16_LIMBS];
ptr_to_u16_limbs(rs1_data, record.rs1_val);
COL_WRITE_ARRAY(row, Rv64LoadAdapterCols, rs1_data, rs1_data);

mem_helper.fill(
row.slice_from(COL_INDEX(Rv64LoadAdapterCols, rs1_aux_cols)),
record.rs1_aux_record.prev_timestamp,
record.from_timestamp
);
mem_helper.fill(
row.slice_from(COL_INDEX(Rv64LoadAdapterCols, read_data_aux)),
record.read_data_aux.prev_timestamp,
record.from_timestamp + 1
);

bool needs_write = record.rd_ptr != UINT32_MAX;
COL_WRITE_VALUE(row, Rv64LoadAdapterCols, rd_ptr, needs_write ? record.rd_ptr : 0);
COL_WRITE_VALUE(row, Rv64LoadAdapterCols, needs_write, needs_write);
if (needs_write) {
mem_helper.fill(
row.slice_from(COL_INDEX(Rv64LoadAdapterCols, write_aux.base)),
record.write_prev_timestamp,
record.from_timestamp + 2
);
Fp prev_data[BLOCK_FE_WIDTH];
copy_u16_cells(prev_data, record.write_prev_data);
COL_WRITE_ARRAY(row, Rv64LoadAdapterCols, write_aux.prev_data, prev_data);
} else {
mem_helper.fill_zero(row.slice_from(COL_INDEX(Rv64LoadAdapterCols, write_aux.base)));
row.fill_zero(COL_INDEX(Rv64LoadAdapterCols, write_aux.prev_data), BLOCK_FE_WIDTH);
}

COL_WRITE_VALUE(row, Rv64LoadAdapterCols, imm, record.imm);
COL_WRITE_VALUE(row, Rv64LoadAdapterCols, imm_sign, record.imm_sign);

uint32_t ptr = rv64_load_effective_ptr(record);
uint32_t ptr_limbs[RV64_PTR_U16_LIMBS];
ptr_to_u16_limbs(ptr_limbs, ptr);
COL_WRITE_ARRAY(row, Rv64LoadAdapterCols, mem_ptr_limbs, ptr_limbs);

uint32_t shift_amount = rv64_load_shift_amount(record);
range_checker.add_count((ptr_limbs[0] - shift_amount) >> 3, U16_BITS - 3);
range_checker.add_count(ptr_limbs[1], pointer_max_bits - U16_BITS);
}
};
122 changes: 0 additions & 122 deletions extensions/riscv/circuit/cuda/include/riscv/adapters/loadstore.cuh

This file was deleted.

105 changes: 105 additions & 0 deletions extensions/riscv/circuit/cuda/include/riscv/adapters/store.cuh
Original file line number Diff line number Diff line change
@@ -0,0 +1,105 @@
#pragma once

#include "primitives/execution.h"
#include "primitives/trace_access.h"
#include "primitives/utils.cuh"
#include "system/memory/controller.cuh"
#include "system/memory/offline_checker.cuh"

using namespace riscv;

template <typename T> struct Rv64StoreAdapterCols {
ExecutionState<T> from_state;
T rs1_ptr;
T rs1_data[RV64_PTR_U16_LIMBS];
MemoryReadAuxCols<T> rs1_aux_cols;
T rs2_ptr;
MemoryReadAuxCols<T> read_data_aux;
T imm;
T imm_sign;
T mem_ptr_limbs[2];
T mem_as;
MemoryBaseAuxCols<T> write_base_aux;
};

struct Rv64StoreAdapterRecord {
uint32_t from_pc;
uint32_t from_timestamp;

uint32_t rs1_ptr;
uint32_t rs1_val;
MemoryReadAuxRecord rs1_aux_record;

uint32_t rs2_ptr;
MemoryReadAuxRecord read_data_aux;
uint16_t imm;
bool imm_sign;
uint8_t mem_as;

uint32_t write_prev_timestamp;
};

static __device__ __forceinline__ uint32_t
rv64_store_effective_ptr(Rv64StoreAdapterRecord record) {
return record.rs1_val + uint32_t(record.imm) +
uint32_t(record.imm_sign) * (uint32_t(UINT16_MAX) << U16_BITS);
}

static __device__ __forceinline__ uint32_t
rv64_store_shift_amount(Rv64StoreAdapterRecord record) {
return rv64_store_effective_ptr(record) & (RV64_REGISTER_NUM_LIMBS - 1);
}

struct Rv64StoreAdapter {
size_t pointer_max_bits;
VariableRangeChecker range_checker;
MemoryAuxColsFactory mem_helper;

__device__ Rv64StoreAdapter(
size_t pointer_max_bits,
VariableRangeChecker range_checker,
uint32_t timestamp_max_bits
)
: pointer_max_bits(pointer_max_bits), range_checker(range_checker),
mem_helper(range_checker, timestamp_max_bits) {}

__device__ void fill_trace_row(RowSlice row, Rv64StoreAdapterRecord record) {
COL_WRITE_VALUE(row, Rv64StoreAdapterCols, from_state.pc, record.from_pc);
COL_WRITE_VALUE(row, Rv64StoreAdapterCols, from_state.timestamp, record.from_timestamp);
COL_WRITE_VALUE(row, Rv64StoreAdapterCols, rs1_ptr, record.rs1_ptr);

Fp rs1_data[RV64_PTR_U16_LIMBS];
ptr_to_u16_limbs(rs1_data, record.rs1_val);
COL_WRITE_ARRAY(row, Rv64StoreAdapterCols, rs1_data, rs1_data);

mem_helper.fill(
row.slice_from(COL_INDEX(Rv64StoreAdapterCols, rs1_aux_cols)),
record.rs1_aux_record.prev_timestamp,
record.from_timestamp
);
mem_helper.fill(
row.slice_from(COL_INDEX(Rv64StoreAdapterCols, read_data_aux)),
record.read_data_aux.prev_timestamp,
record.from_timestamp + 1
);
mem_helper.fill(
row.slice_from(COL_INDEX(Rv64StoreAdapterCols, write_base_aux)),
record.write_prev_timestamp,
record.from_timestamp + 2
);

COL_WRITE_VALUE(row, Rv64StoreAdapterCols, rs2_ptr, record.rs2_ptr);
COL_WRITE_VALUE(row, Rv64StoreAdapterCols, imm, record.imm);
COL_WRITE_VALUE(row, Rv64StoreAdapterCols, imm_sign, record.imm_sign);
COL_WRITE_VALUE(row, Rv64StoreAdapterCols, mem_as, record.mem_as);

uint32_t ptr = rv64_store_effective_ptr(record);
uint32_t ptr_limbs[RV64_PTR_U16_LIMBS];
ptr_to_u16_limbs(ptr_limbs, ptr);
COL_WRITE_ARRAY(row, Rv64StoreAdapterCols, mem_ptr_limbs, ptr_limbs);

uint32_t shift_amount = rv64_store_shift_amount(record);
range_checker.add_count((ptr_limbs[0] - shift_amount) >> 3, U16_BITS - 3);
range_checker.add_count(ptr_limbs[1], pointer_max_bits - U16_BITS);
}
};
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