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hkasivis
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drm/amdgpu: Set snoop bit for SDMA for MI series
[ Upstream commit 3394b1f ] SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for this to happen. v2: Missed a few mmhub_v9_4. Added now. v3: Calculate hub offset once since it doesn't change inside the loop Modified function names based on review comments. Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> (cherry picked from commit ab83ed96f7587d8294068044206438ae6b8c2f27)
1 parent b2d2eec commit 22de28b

5 files changed

Lines changed: 163 additions & 0 deletions

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‎drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,30 @@ static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
172172
WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
173173
}
174174

175+
/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */
176+
static void mmhub_v1_7_init_snoop_override_regs(struct amdgpu_device *adev)
177+
{
178+
uint32_t tmp;
179+
int i;
180+
uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -
181+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;
182+
183+
for (i = 0; i < 5; i++) { /* DAGB instances */
184+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
185+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance);
186+
tmp |= (1 << 15); /* SDMA client is BIT15 */
187+
WREG32_SOC15_OFFSET(MMHUB, 0,
188+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, i * distance, tmp);
189+
190+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
191+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance);
192+
tmp |= (1 << 15);
193+
WREG32_SOC15_OFFSET(MMHUB, 0,
194+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, i * distance, tmp);
195+
}
196+
197+
}
198+
175199
static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
176200
{
177201
uint32_t tmp;
@@ -337,6 +361,7 @@ static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
337361
mmhub_v1_7_init_system_aperture_regs(adev);
338362
mmhub_v1_7_init_tlb_regs(adev);
339363
mmhub_v1_7_init_cache_regs(adev);
364+
mmhub_v1_7_init_snoop_override_regs(adev);
340365

341366
mmhub_v1_7_enable_system_domain(adev);
342367
mmhub_v1_7_disable_identity_aperture(adev);

‎drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,32 @@ static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
213213
}
214214
}
215215

216+
/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */
217+
static void mmhub_v1_8_init_snoop_override_regs(struct amdgpu_device *adev)
218+
{
219+
uint32_t tmp, inst_mask;
220+
int i, j;
221+
uint32_t distance = regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -
222+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;
223+
224+
inst_mask = adev->aid_mask;
225+
for_each_inst(i, inst_mask) {
226+
for (j = 0; j < 5; j++) { /* DAGB instances */
227+
tmp = RREG32_SOC15_OFFSET(MMHUB, i,
228+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance);
229+
tmp |= (1 << 15); /* SDMA client is BIT15 */
230+
WREG32_SOC15_OFFSET(MMHUB, i,
231+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, j * distance, tmp);
232+
233+
tmp = RREG32_SOC15_OFFSET(MMHUB, i,
234+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance);
235+
tmp |= (1 << 15);
236+
WREG32_SOC15_OFFSET(MMHUB, i,
237+
regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, j * distance, tmp);
238+
}
239+
}
240+
}
241+
216242
static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
217243
{
218244
uint32_t tmp, inst_mask;
@@ -418,6 +444,7 @@ static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)
418444
mmhub_v1_8_init_system_aperture_regs(adev);
419445
mmhub_v1_8_init_tlb_regs(adev);
420446
mmhub_v1_8_init_cache_regs(adev);
447+
mmhub_v1_8_init_snoop_override_regs(adev);
421448

422449
mmhub_v1_8_enable_system_domain(adev);
423450
mmhub_v1_8_disable_identity_aperture(adev);

‎drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -198,6 +198,36 @@ static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
198198
hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
199199
}
200200

201+
/* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */
202+
static void mmhub_v9_4_init_snoop_override_regs(struct amdgpu_device *adev, int hubid)
203+
{
204+
uint32_t tmp;
205+
int i;
206+
uint32_t distance = mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE -
207+
mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE;
208+
uint32_t huboffset = hubid * MMHUB_INSTANCE_REGISTER_OFFSET;
209+
210+
for (i = 0; i < 5 - (2 * hubid); i++) {
211+
/* DAGB instances 0 to 4 are in hub0 and 5 to 7 are in hub1 */
212+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
213+
mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE,
214+
huboffset + i * distance);
215+
tmp |= (1 << 15); /* SDMA client is BIT15 */
216+
WREG32_SOC15_OFFSET(MMHUB, 0,
217+
mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE,
218+
huboffset + i * distance, tmp);
219+
220+
tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
221+
mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE,
222+
huboffset + i * distance);
223+
tmp |= (1 << 15);
224+
WREG32_SOC15_OFFSET(MMHUB, 0,
225+
mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE,
226+
huboffset + i * distance, tmp);
227+
}
228+
229+
}
230+
201231
static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
202232
{
203233
uint32_t tmp;
@@ -392,6 +422,7 @@ static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
392422
if (!amdgpu_sriov_vf(adev))
393423
mmhub_v9_4_init_cache_regs(adev, i);
394424

425+
mmhub_v9_4_init_snoop_override_regs(adev, i);
395426
mmhub_v9_4_enable_system_domain(adev, i);
396427
if (!amdgpu_sriov_vf(adev))
397428
mmhub_v9_4_disable_identity_aperture(adev, i);

‎drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -203,6 +203,10 @@
203203
#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1
204204
#define mmDAGB0_WR_MISC_CREDIT 0x0058
205205
#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1
206+
#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005b
207+
#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
208+
#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005c
209+
#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
206210
#define mmDAGB0_WRCLI_ASK_PENDING 0x005d
207211
#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1
208212
#define mmDAGB0_WRCLI_GO_PENDING 0x005e
@@ -455,6 +459,10 @@
455459
#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 1
456460
#define mmDAGB1_WR_MISC_CREDIT 0x00d8
457461
#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 1
462+
#define mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0x00db
463+
#define mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
464+
#define mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x00dc
465+
#define mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
458466
#define mmDAGB1_WRCLI_ASK_PENDING 0x00dd
459467
#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1
460468
#define mmDAGB1_WRCLI_GO_PENDING 0x00de
@@ -707,6 +715,10 @@
707715
#define mmDAGB2_WR_DATA_CREDIT_BASE_IDX 1
708716
#define mmDAGB2_WR_MISC_CREDIT 0x0158
709717
#define mmDAGB2_WR_MISC_CREDIT_BASE_IDX 1
718+
#define mmDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0x015b
719+
#define mmDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
720+
#define mmDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x015c
721+
#define mmDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
710722
#define mmDAGB2_WRCLI_ASK_PENDING 0x015d
711723
#define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX 1
712724
#define mmDAGB2_WRCLI_GO_PENDING 0x015e
@@ -959,6 +971,10 @@
959971
#define mmDAGB3_WR_DATA_CREDIT_BASE_IDX 1
960972
#define mmDAGB3_WR_MISC_CREDIT 0x01d8
961973
#define mmDAGB3_WR_MISC_CREDIT_BASE_IDX 1
974+
#define mmDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0x01db
975+
#define mmDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
976+
#define mmDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x01dc
977+
#define mmDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
962978
#define mmDAGB3_WRCLI_ASK_PENDING 0x01dd
963979
#define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX 1
964980
#define mmDAGB3_WRCLI_GO_PENDING 0x01de
@@ -1211,6 +1227,10 @@
12111227
#define mmDAGB4_WR_DATA_CREDIT_BASE_IDX 1
12121228
#define mmDAGB4_WR_MISC_CREDIT 0x0258
12131229
#define mmDAGB4_WR_MISC_CREDIT_BASE_IDX 1
1230+
#define mmDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0x025b
1231+
#define mmDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
1232+
#define mmDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x025c
1233+
#define mmDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
12141234
#define mmDAGB4_WRCLI_ASK_PENDING 0x025d
12151235
#define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX 1
12161236
#define mmDAGB4_WRCLI_GO_PENDING 0x025e
@@ -4793,6 +4813,10 @@
47934813
#define mmDAGB5_WR_DATA_CREDIT_BASE_IDX 1
47944814
#define mmDAGB5_WR_MISC_CREDIT 0x3058
47954815
#define mmDAGB5_WR_MISC_CREDIT_BASE_IDX 1
4816+
#define mmDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0x305b
4817+
#define mmDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
4818+
#define mmDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x305c
4819+
#define mmDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
47964820
#define mmDAGB5_WRCLI_ASK_PENDING 0x305d
47974821
#define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX 1
47984822
#define mmDAGB5_WRCLI_GO_PENDING 0x305e
@@ -5045,6 +5069,10 @@
50455069
#define mmDAGB6_WR_DATA_CREDIT_BASE_IDX 1
50465070
#define mmDAGB6_WR_MISC_CREDIT 0x30d8
50475071
#define mmDAGB6_WR_MISC_CREDIT_BASE_IDX 1
5072+
#define mmDAGB6_WRCLI_GPU_SNOOP_OVERRIDE 0x30db
5073+
#define mmDAGB6_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
5074+
#define mmDAGB6_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x30dc
5075+
#define mmDAGB6_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
50485076
#define mmDAGB6_WRCLI_ASK_PENDING 0x30dd
50495077
#define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX 1
50505078
#define mmDAGB6_WRCLI_GO_PENDING 0x30de
@@ -5297,6 +5325,10 @@
52975325
#define mmDAGB7_WR_DATA_CREDIT_BASE_IDX 1
52985326
#define mmDAGB7_WR_MISC_CREDIT 0x3158
52995327
#define mmDAGB7_WR_MISC_CREDIT_BASE_IDX 1
5328+
#define mmDAGB7_WRCLI_GPU_SNOOP_OVERRIDE 0x315b
5329+
#define mmDAGB7_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1
5330+
#define mmDAGB7_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x315c
5331+
#define mmDAGB7_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1
53005332
#define mmDAGB7_WRCLI_ASK_PENDING 0x315d
53015333
#define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX 1
53025334
#define mmDAGB7_WRCLI_GO_PENDING 0x315e

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