gpio: phytium: Add wakeup source support for GPIO driver

This patch supports irq_set_wake for phytium GPIO driver. It
allows GPIOs to be configured as wakeup sources and
wake the system from suspend.

Mainline: Open-Source
Signed-off-by: Cui Fulong <cuifulong2112@phytium.com.cn>
Signed-off-by: Li Yuze <liyuze@phytium.com.cn>
Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>

Author: newearth-ss

drivers/gpio/gpio-phytium-core.c

@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/bitops.h>
 #include <linux/seq_file.h>
+#include <linux/interrupt.h>
 
 #include "gpio-phytium-core.h"
 
@@ -378,6 +379,35 @@ int phytium_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 }
 EXPORT_SYMBOL_GPL(phytium_gpio_get_direction);
 
+int phytium_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+	struct phytium_gpio *gpio = gpiochip_get_data(gc);
+	struct phytium_gpio_ctx *ctx = &gpio->ctx;
+	irq_hw_number_t bit = irqd_to_hwirq(d);
+	int ret;
+
+	if (gpio->irq[bit])
+		ret = irq_set_irq_wake(gpio->irq[bit], enable);
+	else
+		ret = irq_set_irq_wake(gpio->irq[0], enable);
+
+	if (ret < 0)
+		dev_err(gc->parent, "set gpio irq wake failed!\n");
+
+	if (enable) {
+		ctx->wake_en |= BIT(bit);
+		if (gpio->is_resuming == 1) {
+			writel(~ctx->wake_en, gpio->regs + GPIO_INTMASK);
+			writel(ctx->wake_en, gpio->regs + GPIO_INTEN);
+		}
+	} else
+		ctx->wake_en &= ~BIT(bit);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(phytium_gpio_irq_set_wake);
+
 int phytium_gpio_irq_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force)
 {
 	int hwirq = irqd_to_hwirq(d);

drivers/gpio/gpio-phytium-core.h

@@ -33,7 +33,7 @@
 #define NGPIO_MAX		32
 #define GPIO_PORT_STRIDE	(GPIO_EXT_PORTB - GPIO_EXT_PORTA)
 
-#define PHYTIUM_GPIO_DRIVER_VERSION "1.1.1"
+#define PHYTIUM_GPIO_DRIVER_VERSION "1.1.2"
 
 struct pin_loc {
 	unsigned int port;
@@ -56,6 +56,7 @@ struct phytium_gpio_ctx {
 	u32 raw_intstatus;
 	u32 ls_sync;
 	u32 debounce;
+	u32 wake_en;
 };
 #endif
 
@@ -86,5 +87,6 @@ void phytium_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p);
 void phytium_gpio_irq_enable(struct irq_data *d);
 void phytium_gpio_irq_disable(struct irq_data *d);
 void phytium_gpio_irq_handler(struct irq_desc *desc);
+int phytium_gpio_irq_set_wake(struct irq_data *d, unsigned int enable);
 int phytium_gpio_irq_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force);
 #endif

drivers/gpio/gpio-phytium-pci.c

@@ -21,6 +21,7 @@ static const struct irq_chip phytium_gpio_irq_chip = {
 	.irq_print_chip		= phytium_gpio_irq_print_chip,
 	.irq_enable		= phytium_gpio_irq_enable,
 	.irq_disable		= phytium_gpio_irq_disable,
+	.irq_set_wake		= phytium_gpio_irq_set_wake,
 	.flags			= IRQCHIP_IMMUTABLE,
 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
@@ -142,7 +143,8 @@ static int phytium_gpio_pci_suspend(struct device *dev)
 	gpio->ctx.int_polarity = readl(gpio->regs + GPIO_INT_POLARITY);
 	gpio->ctx.debounce = readl(gpio->regs + GPIO_DEBOUNCE);
 
-	writel(0, gpio->regs + GPIO_INTEN);
+	writel(~gpio->ctx.wake_en, gpio->regs + GPIO_INTMASK);
+	writel(gpio->ctx.wake_en, gpio->regs + GPIO_INTEN);
 	raw_spin_unlock_irqrestore(&gpio->lock, flags);
 
 	return 0;

drivers/gpio/gpio-phytium-platform.c

@@ -41,6 +41,7 @@ static const struct irq_chip phytium_gpio_irq_chip = {
 	.irq_print_chip		= phytium_gpio_irq_print_chip,
 	.irq_enable		= phytium_gpio_irq_enable,
 	.irq_disable		= phytium_gpio_irq_disable,
+	.irq_set_wake		= phytium_gpio_irq_set_wake,
 	.irq_set_affinity	= phytium_gpio_irq_set_affinity,
 	.flags			= IRQCHIP_IMMUTABLE,
 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
@@ -159,7 +160,8 @@ static int phytium_gpio_suspend(struct device *dev)
 	gpio->ctx.int_polarity = readl(gpio->regs + GPIO_INT_POLARITY);
 	gpio->ctx.debounce = readl(gpio->regs + GPIO_DEBOUNCE);
 
-	writel(0, gpio->regs + GPIO_INTEN);
+	writel(~gpio->ctx.wake_en, gpio->regs + GPIO_INTMASK);
+	writel(gpio->ctx.wake_en, gpio->regs + GPIO_INTEN);
 	raw_spin_unlock_irqrestore(&gpio->lock, flags);
 
 	return 0;