x86/microcode/hygon: Fix microcode loading issue for Hygon processors

The commit ecc031c ("x86/microcode/AMD: Load only SHA256-checksummed
patches") and commit efdb189 ("x86/microcode/AMD: Use the family,
model,stepping encoded in the patch ID") carry a SHA256 checksum for
microcode loading and abandon equivalence table because the family, model
and stepping is part of the microcode patch ID. This results in microcode
loading failure on Hygon family 18h processors because Hygon still uses
equivalence table to verify microcode.

So add equivalence table support for Hygon family 18h processors.

Fixes: efdb189 ("x86/microcode/AMD: Use the family,model,stepping encoded in the patch ID")
Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>

Author: liaoxuan123

arch/x86/kernel/cpu/microcode/amd.c

@@ -216,8 +216,10 @@ static bool verify_sha256_digest(u32 patch_id, u32 cur_rev, const u8 *data, unsi
 	struct sha256_state s;
 	int i;
 
-	if (x86_family(bsp_cpuid_1_eax) < 0x17 ||
-	    x86_family(bsp_cpuid_1_eax) > 0x19)
+	if ((x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	     (x86_family(bsp_cpuid_1_eax) < 0x17 ||
+	      x86_family(bsp_cpuid_1_eax) > 0x19)) ||
+	    x86_cpuid_vendor() == X86_VENDOR_HYGON)
 		return true;
 
 	if (!need_sha_check(cur_rev))
@@ -280,7 +282,8 @@ static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
 	unsigned int i;
 
 	/* Zen and newer do not need an equivalence table. */
-	if (x86_family(bsp_cpuid_1_eax) >= 0x17)
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17)
 		return 0;
 
 	if (!et || !et->num_entries)
@@ -330,7 +333,8 @@ static bool verify_equivalence_table(const u8 *buf, size_t buf_size)
 		return false;
 
 	/* Zen and newer do not need an equivalence table. */
-	if (x86_family(bsp_cpuid_1_eax) >= 0x17)
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17)
 		return true;
 
 	cont_type = hdr[1];
@@ -486,7 +490,8 @@ static int verify_patch(const u8 *buf, size_t buf_size, u32 *patch_size)
 static bool mc_patch_matches(struct microcode_amd *mc, u16 eq_id)
 {
 	/* Zen and newer do not need an equivalence table. */
-	if (x86_family(bsp_cpuid_1_eax) >= 0x17)
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17)
 		return ucode_rev_to_cpuid(mc->hdr.patch_id).full == bsp_cpuid_1_eax;
 	else
 		return eq_id == mc->hdr.processor_rev_id;
@@ -607,7 +612,9 @@ static bool __apply_microcode_amd(struct microcode_amd *mc, u32 *cur_rev,
 
 	native_wrmsrl(MSR_AMD64_PATCH_LOADER, p_addr);
 
-	if (x86_family(bsp_cpuid_1_eax) == 0x17) {
+	if ((x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	     x86_family(bsp_cpuid_1_eax) == 0x17) ||
+	    x86_cpuid_vendor() == X86_VENDOR_HYGON) {
 		unsigned long p_addr_end = p_addr + psize - 1;
 
 		invlpg(p_addr);
@@ -658,9 +665,15 @@ static bool __init find_blobs_in_containers(struct cpio_data *ret)
 {
 	struct cpio_data cp;
 	bool found;
+	const char *path;
+
+	if (x86_cpuid_vendor() == X86_VENDOR_HYGON)
+		path = "kernel/x86/microcode/HygonGenuine.bin";
+	else
+		path = ucode_path;
 
 	if (!get_builtin_microcode(&cp))
-		cp = find_microcode_in_initrd(ucode_path);
+		cp = find_microcode_in_initrd(path);
 
 	found = cp.data && cp.size;
 	if (found)
@@ -728,7 +741,8 @@ static inline bool patch_cpus_equivalent(struct ucode_patch *p,
 					 bool ignore_stepping)
 {
 	/* Zen and newer hardcode the f/m/s in the patch ID */
-        if (x86_family(bsp_cpuid_1_eax) >= 0x17) {
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17) {
 		union cpuid_1_eax p_cid = ucode_rev_to_cpuid(p->patch_id);
 		union cpuid_1_eax n_cid = ucode_rev_to_cpuid(n->patch_id);
 
@@ -754,7 +768,8 @@ static struct ucode_patch *cache_find_patch(struct ucode_cpu_info *uci, u16 equi
 	n.equiv_cpu = equiv_cpu;
 	n.patch_id  = uci->cpu_sig.rev;
 
-	WARN_ON_ONCE(!n.patch_id);
+	if (x86_cpuid_vendor() != X86_VENDOR_HYGON)
+		WARN_ON_ONCE(!n.patch_id);
 
 	list_for_each_entry(p, &microcode_cache, plist)
 		if (patch_cpus_equivalent(p, &n, false))
@@ -766,7 +781,8 @@ static struct ucode_patch *cache_find_patch(struct ucode_cpu_info *uci, u16 equi
 static inline int patch_newer(struct ucode_patch *p, struct ucode_patch *n)
 {
 	/* Zen and newer hardcode the f/m/s in the patch ID */
-        if (x86_family(bsp_cpuid_1_eax) >= 0x17) {
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17) {
 		union zen_patch_rev zp, zn;
 
 		zp.ucode_rev = p->patch_id;
@@ -826,7 +842,9 @@ static struct ucode_patch *find_patch(unsigned int cpu)
 
 	uci->cpu_sig.rev = get_patch_level();
 
-	if (x86_family(bsp_cpuid_1_eax) < 0x17) {
+	if ((x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	     x86_family(bsp_cpuid_1_eax) < 0x17) ||
+	    x86_cpuid_vendor() == X86_VENDOR_HYGON) {
 		equiv_id = find_equiv_id(&equiv_table, uci->cpu_sig.sig);
 		if (!equiv_id)
 			return NULL;
@@ -941,7 +959,8 @@ static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
 	equiv_tbl_len = hdr[2];
 
 	/* Zen and newer do not need an equivalence table. */
-	if (x86_family(bsp_cpuid_1_eax) >= 0x17)
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17)
 		goto out;
 
 	equiv_table.entry = vmalloc(equiv_tbl_len);
@@ -960,7 +979,8 @@ static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
 
 static void free_equiv_cpu_table(void)
 {
-	if (x86_family(bsp_cpuid_1_eax) >= 0x17)
+	if (x86_cpuid_vendor() == X86_VENDOR_AMD &&
+	    x86_family(bsp_cpuid_1_eax) >= 0x17)
 		return;
 
 	vfree(equiv_table.entry);
@@ -1106,7 +1126,9 @@ static int __init save_microcode_in_initrd(void)
 	enum ucode_state ret;
 	struct cpio_data cp;
 
-	if (dis_ucode_ldr || (c->x86_vendor != X86_VENDOR_AMD && c->x86_vendor != X86_VENDOR_HYGON) || c->x86 < 0x10)
+	if (dis_ucode_ldr ||
+	    (c->x86_vendor != X86_VENDOR_AMD && c->x86_vendor != X86_VENDOR_HYGON) ||
+	    (c->x86_vendor == X86_VENDOR_AMD && c->x86 < 0x10))
 		return 0;
 
 	if (!find_blobs_in_containers(&cp))

arch/x86/kernel/cpu/microcode/core.c

@@ -190,7 +190,7 @@ void load_ucode_ap(void)
 			load_ucode_amd_ap(cpuid_1_eax);
 		break;
 	case X86_VENDOR_HYGON:
-		load_ucode_amd_bsp(&early_data, cpuid_1_eax);
+		load_ucode_amd_ap(cpuid_1_eax);
 		break;
 	default:
 		break;