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feat(native): port Verilog extractor to Rust #556

feat(native): port Verilog extractor to Rust

feat(native): port Verilog extractor to Rust #556

Triggered via pull request May 14, 2026 04:48
Status Failure
Total duration 4m 2s
Artifacts 5

build-native.yml

on: pull_request
Matrix: build
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1 error and 1 notice
Build x86_64-apple-darwin
Process completed with exit code 1.
Build x86_64-pc-windows-msvc
NOTICE: windows-2025 requests are being redirected to windows-2025-vs2026 by May 12, 2026

Artifacts

Produced during runtime
Name Size Digest
native-darwin-arm64
9.6 MB
sha256:1173420852e1eb7c10d0e76eeea1d73f405dacdb2b1438a45a7ce20d473f97dc
native-linux-arm64
9.4 MB
sha256:ebace7a8dea14e5b5f9b85efc40301350b36f477084e381172fb17aa3f4088c0
native-linux-x64
9.48 MB
sha256:f5f34318a3fd87563de892065c9d2e78d3f5bc81197a55376afc7d1bbf8b56e2
native-linux-x64-musl
9.55 MB
sha256:921370dce98c175d6fbf28fd3c1da377c1a08ce0822a4a624a49dfe6b3b2f86d
native-win32-x64
8.96 MB
sha256:08293c1f4d2e46dc6e802a783c8f7a744300df68e1d70646bd0b990fed9bf535