Skip to content

feat(native): port Verilog extractor to Rust #3002

feat(native): port Verilog extractor to Rust

feat(native): port Verilog extractor to Rust #3002

Triggered via pull request May 14, 2026 11:01
Status Success
Total duration 38s
Artifacts 1
License Compliance Scan
28s
License Compliance Scan
Fit to window
Zoom out
Zoom in

Artifacts

Produced during runtime
Name Size Digest
license-compliance-reports
24.6 KB
sha256:4aa1b28501c190dfea7b8c4c0139cc7d2de7a98e0ac2c832d1985755e040a219