Committed minor changes to try and debug

Committed minor changes from small attempts to
debug failing `make run-precheck`. Specifically,
before changing the netlist in `verilog/gl/user_project_wrapper.v`,
`make run-precheck` would completely fail on `Consistency`
due to lack of power pins in the netlist. After
manually adding those power pins, now the design
fails on `LVS`, `OEB`, and `XOR`.

Author: marcuspartcl

verilog/dv/cocotb/design_info.yaml

@@ -1,8 +1,8 @@
-CARAVEL_ROOT: /home/marcus/caravel_rtl_fix/caravel
-MCW_ROOT: /home/marcus/caravel_rtl_fix/mgmt_core_wrapper
+CARAVEL_ROOT: /home/marcus/caravel_user_neuromorphic_comp/caravel
+MCW_ROOT: /home/marcus/caravel_user_neuromorphic_comp/mgmt_core_wrapper
 PDK: sky130A
-PDK_ROOT: /home/marcus/caravel_rtl_fix/dependencies/pdks
-USER_PROJECT_ROOT: /home/marcus/caravel_rtl_fix
+PDK_ROOT: /home/marcus/caravel_user_neuromorphic_comp/dependencies/pdks
+USER_PROJECT_ROOT: /home/marcus/caravel_user_neuromorphic_comp
 caravan: false
 clk: 25
 emailto: