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update port maps through Register for Process
1 parent 89c22f2 commit 1427465

1 file changed

Lines changed: 19 additions & 14 deletions

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src/pathsim_chem/tritium/residencetime.py

Lines changed: 19 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
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import numpy as np
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from pathsim.blocks.dynsys import DynamicalSystem
12-
12+
from pathsim.utils.register import Register
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# BLOCKS ================================================================================
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@@ -50,30 +50,35 @@ class ResidenceTime(DynamicalSystem):
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def __init__(self, tau=1, betas=None, gammas=None, initial_value=0, source_term=0):
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53-
#input validation
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# input validation
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if np.isclose(tau, 0):
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raise ValueError(f"'tau' must be nonzero but is {tau}")
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57-
#time constant and input/output weights
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# time constant and input/output weights
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self.tau = tau
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self.betas = 1 if betas is None else np.array(betas)
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self.gammas = 1 if gammas is None else np.array(gammas)
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self.source_term = source_term
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63-
#rhs of residence time ode
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# rhs of residence time ode
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def _fn_d(x, u, t):
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return -x/self.tau + self.source_term + sum(self.betas*u)
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67-
#jacobian of rhs wrt x
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# jacobian of rhs wrt x
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def _jc_d(x, u, t):
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return -1/self.tau
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71-
#output function of residence time ode
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# output function of residence time ode
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def _fn_a(x, u, t):
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return self.gammas * x
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75-
#initialization just like `DynamicalSystem` block
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super().__init__(func_dyn=_fn_d, jac_dyn=_jc_d, func_alg=_fn_a, initial_value=initial_value)
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# initialization just like `DynamicalSystem` block
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super().__init__(
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func_dyn=_fn_d,
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jac_dyn=_jc_d,
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func_alg=_fn_a,
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initial_value=initial_value,
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)
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class Process(ResidenceTime):
@@ -112,11 +117,11 @@ class Process(ResidenceTime):
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constant source term / generation term of the process
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"""
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115-
#max number of ports
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_n_out_max = 2
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118-
#maps for input and output port labels
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_port_map_out = {"x": 0, "x/tau": 1}
120-
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def __init__(self, tau=1, initial_value=0, source_term=0):
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super().__init__(tau, 1, [1, 1/tau], initial_value, source_term)
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# define output port maps based on fractions
124+
self.outputs = Register(
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size=2,
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mapping={"x": 0, "x/tau": 1}
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)

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