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added proper mappings to all blocks
1 parent 4354ad9 commit f9ae0cb

1 file changed

Lines changed: 35 additions & 20 deletions

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src/python/custom_pathsim_blocks.py

Lines changed: 35 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
class Process(ODE):
88
name_to_output_port = {"inv": 0, "mass_flow_rate": 1}
9+
_port_map_out = {"inv": 0, "mass_flow_rate": 1}
910

1011
def __init__(self, residence_time=0, initial_value=0, source_term=0):
1112
alpha = -1 / residence_time if residence_time != 0 else 0
@@ -25,8 +26,8 @@ def update(self, t):
2526
mass_rate = x / self.residence_time
2627
# first output is the inv, second is the mass_flow_rate
2728
outputs = [None, None]
28-
outputs[self.name_to_output_port["inv"]] = x
29-
outputs[self.name_to_output_port["mass_flow_rate"]] = mass_rate
29+
outputs[self._port_map_out["inv"]] = x
30+
outputs[self._port_map_out["mass_flow_rate"]] = mass_rate
3031
# update the outputs
3132
self.outputs.update_from_array(outputs)
3233

@@ -48,6 +49,7 @@ def update(self, t):
4849

4950
class Splitter2(Splitter):
5051
name_to_output_port = {"source1": 0, "source2": 1}
52+
_port_map_out = {"source1": 0, "source2": 1}
5153

5254
def __init__(self, f1=0.5, f2=0.5):
5355
"""
@@ -58,6 +60,7 @@ def __init__(self, f1=0.5, f2=0.5):
5860

5961
class Splitter3(Splitter):
6062
name_to_output_port = {"source1": 0, "source2": 1, "source3": 2}
63+
_port_map_out = {"source1": 0, "source2": 1, "source3": 2}
6164

6265
def __init__(self, f1=1 / 3, f2=1 / 3, f3=1 / 3):
6366
"""
@@ -126,6 +129,17 @@ class Bubbler(Subsystem):
126129
"vial4": 3,
127130
"sample_out": 4,
128131
}
132+
_port_map_out = {
133+
"vial1": 0,
134+
"vial2": 1,
135+
"vial3": 2,
136+
"vial4": 3,
137+
"sample_out": 4,
138+
}
139+
_port_map_in = {
140+
"sample_in_soluble": 0,
141+
"sample_in_insoluble": 1,
142+
}
129143

130144
def __init__(
131145
self,
@@ -183,7 +197,7 @@ def __init__(
183197
]
184198
connections = [
185199
Connection(
186-
interface[self.name_to_input_port["sample_in_soluble"]], col_eff1
200+
interface[self._port_map_in["sample_in_soluble"]], col_eff1
187201
),
188202
Connection(col_eff1[0], vial_1),
189203
Connection(col_eff1[1], col_eff2),
@@ -192,18 +206,18 @@ def __init__(
192206
Connection(conversion_eff[0], add1[0]),
193207
Connection(conversion_eff[1], add2[0]),
194208
Connection(
195-
interface[self.name_to_input_port["sample_in_insoluble"]], add1[1]
209+
interface[self._port_map_in["sample_in_insoluble"]], add1[1]
196210
),
197211
Connection(add1, col_eff3),
198212
Connection(col_eff3[0], vial_3),
199213
Connection(col_eff3[1], col_eff4),
200214
Connection(col_eff4[0], vial_4),
201215
Connection(col_eff4[1], add2[1]),
202-
Connection(vial_1, interface[self.name_to_output_port["vial1"]]),
203-
Connection(vial_2, interface[self.name_to_output_port["vial2"]]),
204-
Connection(vial_3, interface[self.name_to_output_port["vial3"]]),
205-
Connection(vial_4, interface[self.name_to_output_port["vial4"]]),
206-
Connection(add2, interface[self.name_to_output_port["sample_out"]]),
216+
Connection(vial_1, interface[self._port_map_out["vial1"]]),
217+
Connection(vial_2, interface[self._port_map_out["vial2"]]),
218+
Connection(vial_3, interface[self._port_map_out["vial3"]]),
219+
Connection(vial_4, interface[self._port_map_out["vial4"]]),
220+
Connection(add2, interface[self._port_map_out["sample_out"]]),
207221
]
208222
super().__init__(blocks, connections)
209223

@@ -262,17 +276,20 @@ class FestimWall(Block):
262276
name_to_output_port = {"flux_0": 0, "flux_L": 1}
263277
name_to_input_port = {"c_0": 0, "c_L": 1}
264278

279+
_port_map_out = {"flux_0": 0, "flux_L": 1}
280+
_port_map_in = {"c_0": 0, "c_L": 1}
281+
265282
def __init__(
266283
self, thickness, temperature, D_0, E_D, surface_area=1, n_vertices=100
267284
):
268-
super().__init__()
269285
try:
270286
import festim as F
271287
except ImportError:
272288
raise ImportError("festim is needed for FestimWall node.")
289+
super().__init__()
273290

274-
self.inputs = Register(size=2)
275-
self.outputs = Register(size=2)
291+
self.inputs = Register(size=2, mapping=self._port_map_in)
292+
self.outputs = Register(size=2, mapping=self._port_map_out)
276293

277294
self.thickness = thickness
278295
self.temperature = temperature
@@ -345,10 +362,8 @@ def update(self, t):
345362
# return 0.0
346363

347364
# block inputs
348-
inputs = self.inputs.to_array()
349-
c_0 = inputs[self.name_to_input_port["c_0"]]
350-
c_L = inputs[self.name_to_input_port["c_L"]]
351-
# print(c_0, c_L)
365+
c_0 = self.inputs["c_0"]
366+
c_L = self.inputs["c_L"]
352367

353368
if t == 0.0:
354369
flux_0, flux_L = 0, 0
@@ -359,7 +374,7 @@ def update(self, t):
359374

360375
flux_0 *= self.surface_area
361376
flux_L *= self.surface_area
362-
outputs = [None, None]
363-
outputs[self.name_to_output_port["flux_0"]] = flux_0
364-
outputs[self.name_to_output_port["flux_L"]] = flux_L
365-
return self.outputs.update_from_array(outputs)
377+
378+
self.outputs["flux_0"] = flux_0
379+
self.outputs["flux_L"] = flux_L
380+
return self.outputs

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