Why

Turbo-Run-Length-Encoding already has a generic scalar implementation, but riscv64 was still only covered implicitly and could fall back to host-oriented assumptions in two places:

• the makefile did not recognize riscv64 / riscv32, so cross builds could still inherit x86-oriented defaults such as -march=native and -mssse3;
• include_/conf.h relied on architecture checks that, under a forced-RISC-V validation build on MinGW, could still be short-circuited by host macros before reaching a RISC-V-safe unaligned-access path.

In addition, a few write sites assumed helpers like ctou16 / ctou32 were lvalues, which does not hold once the RISC-V path uses memcpy-style accessors.

This patch makes the existing scalar path explicit and verifiable for RISC-V without adding RVV intrinsics or changing the current x86 / ARM optimized paths.

What changed

• Updated makefile:
  • detect riscv64 / riscv32 from the compiler name;
  • avoid injecting x86-specific defaults such as -march=native and -mssse3 for RISC-V targets.
• Updated include_/conf.h:
  • add an explicit RISC-V unaligned-access branch ahead of host-x86 fallback checks;
  • provide memcpy-based ctou16/32/64, ctof32/64, stou8/16/32/64, stof32/64, and ltou32/64;
  • mark __riscv_xlen == 64 as a 64-bit target for __WORDSIZE.
• Updated include_/time_.h:
  • keep forced-RISC-V smoke builds on a conservative timer path instead of inheriting _WIN32-specific assumptions.
• Updated trle_.h:
  • replace variable-length encoding write sites that used ctou16 / ctou32 as lvalues with stou16 / stou32.
• Updated trled.c:
  • replace generic write sites with stou32 / stou64 / T2(stou, USIZE) so the scalar RISC-V path remains valid.
• Updated README.md:
  • document that Linux riscv64 currently uses the scalar fallback path.

Verification

• Ran native build successfully:
  • gmake
• Ran simulated riscv64 dry-run successfully:
  • gmake -n ARCH=riscv64 CC=riscv64-linux-gnu-gcc
• Confirmed the simulated riscv64 dry-run:
  • does not inject -march=native;
  • does not inject -mssse3.
• Confirmed forced-RISC-V macros in conf.h:
  • gcc -E -dM -D__riscv=1 -D__riscv_xlen=64 -U__x86_64__ -U__amd64__ -U__aarch64__ -U__ARM_NEON -U__AVX2__ -U__AVX__ -U__SSE4_1__ -U__SSSE3__ -U__SSE3__ -U__SSE2__ -U__SSE__ -U__LP64__ -U_LP64 -U_WIN64 -U_M_X64 macro_probe.c
  • verified ctou16/32/64, stou8/16/32/64, and __WORDSIZE 64 are defined under forced __riscv.
• Ran forced-RISC-V source compiles successfully:
  • gcc -c -D__riscv=1 -D__riscv_xlen=64 -U__x86_64__ -U__amd64__ -U__aarch64__ -U__ARM_NEON -U__AVX2__ -U__AVX__ -U__SSE4_1__ -U__SSSE3__ -U__SSE3__ -U__SSE2__ -U__SSE__ -U__LP64__ -U_LP64 -U_WIN64 -U_M_X64 trlec.c -o NUL
  • gcc -c -D__riscv=1 -D__riscv_xlen=64 -U__x86_64__ -U__amd64__ -U__aarch64__ -U__ARM_NEON -U__AVX2__ -U__AVX__ -U__SSE4_1__ -U__SSSE3__ -U__SSE3__ -U__SSE2__ -U__SSE__ -U__LP64__ -U_LP64 -U_WIN64 -U_M_X64 trled.c -o NUL
  • gcc -c -D__riscv=1 -D__riscv_xlen=64 -U__x86_64__ -U__amd64__ -U__aarch64__ -U__ARM_NEON -U__AVX2__ -U__AVX__ -U__SSE4_1__ -U__SSSE3__ -U__SSE3__ -U__SSE2__ -U__SSE__ -U__LP64__ -U_LP64 -U_WIN64 -U_M_X64 trle.c -o NUL
• Ran a full forced-RISC-V make successfully:
  • gmake ARCH=riscv64 "CC=gcc -D__riscv=1 -D__riscv_xlen=64 -U__x86_64__ -U__amd64__ -U__aarch64__ -U__ARM_NEON -U__AVX2__ -U__AVX__ -U__SSE4_1__ -U__SSSE3__ -U__SSE3__ -U__SSE2__ -U__SSE__ -U__LP64__ -U_LP64 -U_WIN64 -U_M_X64"
• Verified a real riscv64 executable in dockcross/linux-riscv64:20260515-5fd14ac:
  • built trle with make ARCH=riscv64 CC=/usr/xcc/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-gcc;
  • confirmed trle with file and readelf -h, which reported a real RISC-V ELF (Machine: RISC-V);
  • confirmed the real build log contains no -march=native or -mssse3;
  • ran trle -e 1 sample.bin under qemu-riscv64 and got a successful encode/decode round-trip with no ERROR output;
  • ran the default all-algorithm mode under qemu-riscv64 on the same sample file and again saw no ERROR, covering trle, srle, mrle, and the memcpy baseline path.

Notes

• This is a conservative portability patch. It does not add RVV kernels or RISC-V-specific performance tuning.
• The goal is to make the existing scalar implementation explicit, buildable, and verifiable for riscv64.