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Commit abc25a1

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FlyGoatgregkh
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irqchip/mips-gic: Use raw spinlock for gic_lock
[ Upstream commit 3d6a0e4197c04599d75d85a608c8bb16a630a38c ] Since we may hold gic_lock in hardirq context, use raw spinlock makes more sense given that it is for low-level interrupt handling routine and the critical section is small. Fixes BUG: [ 0.426106] ============================= [ 0.426257] [ BUG: Invalid wait context ] [ 0.426422] 6.3.0-rc7-next-20230421-dirty #54 Not tainted [ 0.426638] ----------------------------- [ 0.426766] swapper/0/1 is trying to lock: [ 0.426954] ffffffff8104e7b8 (gic_lock){....}-{3:3}, at: gic_set_type+0x30/08 Fixes: 95150ae ("irqchip: mips-gic: Implement irq_set_type callback") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Tested-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230424103156.66753-3-jiaxun.yang@flygoat.com Signed-off-by: Sasha Levin <sashal@kernel.org>
1 parent 05de606 commit abc25a1

1 file changed

Lines changed: 15 additions & 15 deletions

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drivers/irqchip/irq-mips-gic.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ void __iomem *mips_gic_base;
4848

4949
DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
5050

51-
static DEFINE_SPINLOCK(gic_lock);
51+
static DEFINE_RAW_SPINLOCK(gic_lock);
5252
static struct irq_domain *gic_irq_domain;
5353
static struct irq_domain *gic_ipi_domain;
5454
static int gic_shared_intrs;
@@ -207,7 +207,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
207207

208208
irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
209209

210-
spin_lock_irqsave(&gic_lock, flags);
210+
raw_spin_lock_irqsave(&gic_lock, flags);
211211
switch (type & IRQ_TYPE_SENSE_MASK) {
212212
case IRQ_TYPE_EDGE_FALLING:
213213
pol = GIC_POL_FALLING_EDGE;
@@ -247,7 +247,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
247247
else
248248
irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
249249
handle_level_irq, NULL);
250-
spin_unlock_irqrestore(&gic_lock, flags);
250+
raw_spin_unlock_irqrestore(&gic_lock, flags);
251251

252252
return 0;
253253
}
@@ -265,7 +265,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
265265
return -EINVAL;
266266

267267
/* Assumption : cpumask refers to a single CPU */
268-
spin_lock_irqsave(&gic_lock, flags);
268+
raw_spin_lock_irqsave(&gic_lock, flags);
269269

270270
/* Re-route this IRQ */
271271
write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
@@ -276,7 +276,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
276276
set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
277277

278278
irq_data_update_effective_affinity(d, cpumask_of(cpu));
279-
spin_unlock_irqrestore(&gic_lock, flags);
279+
raw_spin_unlock_irqrestore(&gic_lock, flags);
280280

281281
return IRQ_SET_MASK_OK;
282282
}
@@ -354,12 +354,12 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
354354
cd = irq_data_get_irq_chip_data(d);
355355
cd->mask = false;
356356

357-
spin_lock_irqsave(&gic_lock, flags);
357+
raw_spin_lock_irqsave(&gic_lock, flags);
358358
for_each_online_cpu(cpu) {
359359
write_gic_vl_other(mips_cm_vp_id(cpu));
360360
write_gic_vo_rmask(BIT(intr));
361361
}
362-
spin_unlock_irqrestore(&gic_lock, flags);
362+
raw_spin_unlock_irqrestore(&gic_lock, flags);
363363
}
364364

365365
static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
@@ -372,12 +372,12 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
372372
cd = irq_data_get_irq_chip_data(d);
373373
cd->mask = true;
374374

375-
spin_lock_irqsave(&gic_lock, flags);
375+
raw_spin_lock_irqsave(&gic_lock, flags);
376376
for_each_online_cpu(cpu) {
377377
write_gic_vl_other(mips_cm_vp_id(cpu));
378378
write_gic_vo_smask(BIT(intr));
379379
}
380-
spin_unlock_irqrestore(&gic_lock, flags);
380+
raw_spin_unlock_irqrestore(&gic_lock, flags);
381381
}
382382

383383
static void gic_all_vpes_irq_cpu_online(void)
@@ -390,7 +390,7 @@ static void gic_all_vpes_irq_cpu_online(void)
390390
unsigned long flags;
391391
int i;
392392

393-
spin_lock_irqsave(&gic_lock, flags);
393+
raw_spin_lock_irqsave(&gic_lock, flags);
394394

395395
for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
396396
unsigned int intr = local_intrs[i];
@@ -402,7 +402,7 @@ static void gic_all_vpes_irq_cpu_online(void)
402402
write_gic_vl_smask(BIT(intr));
403403
}
404404

405-
spin_unlock_irqrestore(&gic_lock, flags);
405+
raw_spin_unlock_irqrestore(&gic_lock, flags);
406406
}
407407

408408
static struct irq_chip gic_all_vpes_local_irq_controller = {
@@ -432,11 +432,11 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
432432

433433
data = irq_get_irq_data(virq);
434434

435-
spin_lock_irqsave(&gic_lock, flags);
435+
raw_spin_lock_irqsave(&gic_lock, flags);
436436
write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
437437
write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
438438
irq_data_update_effective_affinity(data, cpumask_of(cpu));
439-
spin_unlock_irqrestore(&gic_lock, flags);
439+
raw_spin_unlock_irqrestore(&gic_lock, flags);
440440

441441
return 0;
442442
}
@@ -529,12 +529,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
529529
if (!gic_local_irq_is_routable(intr))
530530
return -EPERM;
531531

532-
spin_lock_irqsave(&gic_lock, flags);
532+
raw_spin_lock_irqsave(&gic_lock, flags);
533533
for_each_online_cpu(cpu) {
534534
write_gic_vl_other(mips_cm_vp_id(cpu));
535535
write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
536536
}
537-
spin_unlock_irqrestore(&gic_lock, flags);
537+
raw_spin_unlock_irqrestore(&gic_lock, flags);
538538

539539
return 0;
540540
}

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