@@ -103,6 +103,8 @@ static void xe_info_from_device_id(struct xe_device *xe)
103103
104104 const uint16_t ptl_ids [] = { 0xB080 , 0xB090 , 0xB0A0 , 0xB0B0 , 0xB0FF };
105105
106+ const uint16_t bmg_ids [] = { 0xE20B , 0xE20C , 0xE210 , 0xE211 };
107+
106108 unsigned i ;
107109 xe -> graphics_version = 0 ;
108110 xe -> is_xelpd = false;
@@ -142,6 +144,13 @@ static void xe_info_from_device_id(struct xe_device *xe)
142144 xe -> graphics_version = 12 ;
143145 xe -> is_mtl_or_newer = true;
144146 }
147+
148+ /* BMG */
149+ for (i = 0 ; i < ARRAY_SIZE (bmg_ids ); i ++ )
150+ if (bmg_ids [i ] == xe -> device_id ) {
151+ xe -> graphics_version = 20 ;
152+ xe -> is_mtl_or_newer = true;
153+ }
145154}
146155
147156static void xe_get_modifier_order (struct xe_device * xe )
@@ -702,8 +711,12 @@ static int xe_bo_create_from_metadata(struct bo *bo)
702711 .flags = DRM_XE_GEM_CREATE_FLAG_SCANOUT ,
703712 };
704713
705- /* FIXME: let's assume iGPU with SYSMEM is only supported */
706- gem_create .placement |= BITFIELD_BIT (DRM_XE_MEM_REGION_CLASS_SYSMEM );
714+ if (xe -> has_local_mem ) {
715+ gem_create .placement |= BITFIELD_BIT (DRM_XE_MEM_REGION_CLASS_VRAM );
716+ } else {
717+ gem_create .placement |= BITFIELD_BIT (DRM_XE_MEM_REGION_CLASS_SYSMEM );
718+ }
719+
707720 gem_create .cpu_caching = DRM_XE_GEM_CPU_CACHING_WC ;
708721
709722 ret = drmIoctl (bo -> drv -> fd , DRM_IOCTL_XE_GEM_CREATE , & gem_create );
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