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uyjulianuyjulian
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cleanup: Cleanup cop0 access using inline function
1 parent db9bcdb commit c02f09a

16 files changed

Lines changed: 185 additions & 228 deletions

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‎common/include/mipscopaccess.h‎

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
1+
/**
2+
* @file
3+
* MIPS COP coprocessor access
4+
*/
5+
6+
#ifndef __MIPSCOPACCESS_H__
7+
#define __MIPSCOPACCESS_H__
8+
9+
#include <tamtypes.h>
10+
11+
enum mips_cop0_reg
12+
{
13+
/** Programmable register to select TLB entry for reading or writing (purpose: MMU) */
14+
COP0_REG_Index = 0,
15+
/** Pseudo-random counter for TLB replacement (purpose: MMU) */
16+
COP0_REG_Random = 1,
17+
/** Low half of TLB entry for even PFN (Physical page number) (purpose: MMU) */
18+
COP0_REG_EntryLo0 = 2,
19+
/** Low half of TLB entry for odd PFN (Physical page number) (purpose: MMU) */
20+
COP0_REG_EntryLo1 = 3,
21+
/** Pointer to kernel virtual PTE table (purpose: Exception) */
22+
COP0_REG_Context = 4,
23+
/** Mask that sets the TLB page size (purpose: MMU) */
24+
COP0_REG_PageMask = 5,
25+
/** Number of wired TLB entries (purpose: MMU) */
26+
COP0_REG_Wired = 6,
27+
/** Bad virtual address (purpose: Exception) */
28+
COP0_REG_BadVAddr = 8,
29+
/** Timer compare (purpose: Exception) */
30+
COP0_REG_Count = 9,
31+
/** High half of TLB entry(Virtual page number and ASID) (purpose: MMU) */
32+
COP0_REG_EntryHi = 10,
33+
/** Timer compare (purpose: Exception) */
34+
COP0_REG_Compare = 11,
35+
/** Processor Status Register (purpose: Exception) */
36+
COP0_REG_Status = 12,
37+
/** Cause of the last exception taken (purpose: Exception) */
38+
COP0_REG_Cause = 13,
39+
/** Exception Program Counter (purpose: Exception) */
40+
COP0_REG_EPC = 14,
41+
/** Processor Revision Identifier (purpose: MMU) */
42+
COP0_REG_PRId = 15,
43+
/** Configuration Register (purpose: MMU) */
44+
COP0_REG_Config = 16,
45+
/** Bad Physical Address (purpose: Exception) */
46+
COP0_REG_BadPAddr = 23,
47+
/** This is used for Debug function (purpose: Debug) */
48+
COP0_REG_Debug = 24,
49+
/** Performance Counter and Control Register (purpose: Exception) */
50+
COP0_REG_Perf = 25,
51+
/** Cache Tag register(low bits) (purpose: MMU) */
52+
COP0_REG_TagLo = 28,
53+
/** Cache Tag register(high bits) (purpose: MMU) */
54+
COP0_REG_TagHi = 29,
55+
/** Error Exception Program Counter (purpose: Exception) */
56+
COP0_REG_ErrorPC = 30,
57+
};
58+
59+
static inline __attribute__((__always_inline__)) u32 get_mips_cop_reg(const u32 cop, const u32 idx)
60+
{
61+
u32 val;
62+
63+
__asm__ __volatile__("mfc%[cop]\t%[val], $%[idx]\n" : [val] "=r"(val) : [cop] "i"(cop), [idx] "i"(idx));
64+
return val;
65+
}
66+
67+
static inline void set_mips_cop_reg(const u32 cop, const u32 idx, u32 val)
68+
{
69+
__asm__ __volatile__("mtc%[cop]\t%[val], $%[idx]\n" :: [val] "r"(val), [cop] "i"(cop), [idx] "i"(idx));
70+
}
71+
72+
#endif /* __MIPSCOPACCESS_H__ */

‎ee/kernel/include/kernel.h‎

Lines changed: 15 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include <stddef.h>
2121
#include <stdarg.h>
2222
#include <sifdma.h>
23+
#include <mipscopaccess.h>
2324

2425
#define DI DIntr
2526
#define EI EIntr
@@ -151,50 +152,29 @@ static inline int ee_get_opmode(void)
151152
{
152153
u32 status;
153154

154-
__asm__ __volatile__(
155-
".set\tpush\n\t"
156-
".set\tnoreorder\n\t"
157-
"mfc0\t%0, $12\n\t"
158-
".set\tpop\n\t"
159-
: "=r"(status));
155+
status = get_mips_cop_reg(0, COP0_REG_Status);
160156

161157
return ((status >> 3) & 3);
162158
}
163159

164160
static inline int ee_set_opmode(u32 opmode)
165161
{
166-
u32 status, mask;
167-
168-
__asm__ __volatile__(
169-
".set\tpush\n\t"
170-
".set\tnoreorder\n\t"
171-
"mfc0\t%0, $12\n\t"
172-
"li\t%1, 0xffffffe7\n\t"
173-
"and\t%0, %1\n\t"
174-
"or\t%0, %2\n\t"
175-
"mtc0\t%0, $12\n\t"
176-
"sync.p\n\t"
177-
".set\tpop\n\t"
178-
: "=r"(status), "=r"(mask)
179-
: "r"(opmode));
162+
u32 status;
163+
164+
status = (get_mips_cop_reg(0, COP0_REG_Status) & ~0x18) | opmode;
165+
set_mips_cop_reg(0, COP0_REG_Status, status);
166+
EE_SYNCP();
180167

181168
return ((status >> 3) & 3);
182169
}
183170

184171
static inline int ee_kmode_enter()
185172
{
186-
u32 status, mask;
187-
188-
__asm__ __volatile__(
189-
".set\tpush\n\t"
190-
".set\tnoreorder\n\t"
191-
"mfc0\t%0, $12\n\t"
192-
"li\t%1, 0xffffffe7\n\t"
193-
"and\t%0, %1\n\t"
194-
"mtc0\t%0, $12\n\t"
195-
"sync.p\n\t"
196-
".set\tpop\n\t"
197-
: "=r"(status), "=r"(mask));
173+
u32 status;
174+
175+
status = (get_mips_cop_reg(0, COP0_REG_Status) & ~0x18);
176+
set_mips_cop_reg(0, COP0_REG_Status, status);
177+
EE_SYNCP();
198178

199179
return status;
200180
}
@@ -203,15 +183,9 @@ static inline int ee_kmode_exit()
203183
{
204184
int status;
205185

206-
__asm__ __volatile__(
207-
".set\tpush\n\t"
208-
".set\tnoreorder\n\t"
209-
"mfc0\t%0, $12\n\t"
210-
"ori\t%0, 0x10\n\t"
211-
"mtc0\t%0, $12\n\t"
212-
"sync.p\n\t"
213-
".set\tpop\n\t"
214-
: "=r"(status));
186+
status = get_mips_cop_reg(0, COP0_REG_Status) | 0x10;
187+
set_mips_cop_reg(0, COP0_REG_Status, status);
188+
EE_SYNCP();
215189

216190
return status;
217191
}

‎ee/kernel/src/delaythread.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include <timer.h>
1818
#include <timer_alarm.h>
1919
#include <delaythread.h>
20+
#include <mipscopaccess.h>
2021

2122
#ifdef F_DelayThread
2223
static u64 DelayThreadWakeup_callback(s32 alarm_id, u64 scheduled_time, u64 actual_time, void *arg, void *pc_value)
@@ -38,7 +39,7 @@ s32 DelayThread(s32 microseconds)
3839
s32 timer_alarm_id;
3940
ee_sema_t sema;
4041

41-
__asm__ __volatile__ ("mfc0\t%0, $12" : "=r" (eie));
42+
eie = get_mips_cop_reg(0, COP0_REG_Status);
4243
if ((eie & 0x10000) == 0)
4344
{
4445
return 0x80008008; // ECPUDI

‎ee/kernel/src/glue.c‎

Lines changed: 12 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,14 @@
1414
*/
1515

1616
#include "kernel.h"
17+
#include <mipscopaccess.h>
1718

1819
#ifdef F_DIntr
1920
int DIntr()
2021
{
2122
int eie, res;
2223

23-
__asm__ __volatile__("mfc0\t%0, $12"
24-
: "=r"(eie));
24+
eie = get_mips_cop_reg(0, COP0_REG_Status);
2525
eie &= 0x10000;
2626
res = eie != 0;
2727

@@ -32,8 +32,7 @@ int DIntr()
3232
do {
3333
__asm__ __volatile__("di");
3434
EE_SYNCP();
35-
__asm__ __volatile__("mfc0\t%0, $12"
36-
: "=r"(eie));
35+
eie = get_mips_cop_reg(0, COP0_REG_Status);
3736
eie &= 0x10000;
3837
} while (eie);
3938

@@ -46,8 +45,7 @@ int EIntr()
4645
{
4746
int eie;
4847

49-
__asm__ __volatile__("mfc0\t%0, $12"
50-
: "=r"(eie));
48+
eie = get_mips_cop_reg(0, COP0_REG_Status);
5149
eie &= 0x10000;
5250
__asm__ __volatile__("ei");
5351

@@ -60,8 +58,7 @@ int EnableIntc(int intc)
6058
{
6159
int eie, res;
6260

63-
__asm__ __volatile__("mfc0\t%0, $12"
64-
: "=r"(eie));
61+
eie = get_mips_cop_reg(0, COP0_REG_Status);
6562
eie &= 0x10000;
6663

6764
if (eie)
@@ -82,8 +79,7 @@ int DisableIntc(int intc)
8279
{
8380
int eie, res;
8481

85-
__asm__ __volatile__("mfc0\t%0, $12"
86-
: "=r"(eie));
82+
eie = get_mips_cop_reg(0, COP0_REG_Status);
8783
eie &= 0x10000;
8884

8985
if (eie)
@@ -104,8 +100,7 @@ int EnableDmac(int dmac)
104100
{
105101
int eie, res;
106102

107-
__asm__ __volatile__("mfc0\t%0, $12"
108-
: "=r"(eie));
103+
eie = get_mips_cop_reg(0, COP0_REG_Status);
109104
eie &= 0x10000;
110105

111106
if (eie)
@@ -126,8 +121,7 @@ int DisableDmac(int dmac)
126121
{
127122
int eie, res;
128123

129-
__asm__ __volatile__("mfc0\t%0, $12"
130-
: "=r"(eie));
124+
eie = get_mips_cop_reg(0, COP0_REG_Status);
131125
eie &= 0x10000;
132126

133127
if (eie)
@@ -148,8 +142,7 @@ int SetAlarm(u16 time, void (*callback)(s32 alarm_id, u16 time, void *common), v
148142
{
149143
int eie, res;
150144

151-
__asm__ __volatile__("mfc0\t%0, $12"
152-
: "=r"(eie));
145+
eie = get_mips_cop_reg(0, COP0_REG_Status);
153146
eie &= 0x10000;
154147

155148
if (eie)
@@ -170,8 +163,7 @@ int ReleaseAlarm(int alarm_id)
170163
{
171164
int eie, res;
172165

173-
__asm__ __volatile__("mfc0\t%0, $12"
174-
: "=r"(eie));
166+
eie = get_mips_cop_reg(0, COP0_REG_Status);
175167
eie &= 0x10000;
176168

177169
if (eie)
@@ -252,8 +244,7 @@ void SyncDCache(void *start, void *end)
252244
{
253245
int eie;
254246

255-
__asm__ __volatile__("mfc0\t%0, $12"
256-
: "=r"(eie));
247+
eie = get_mips_cop_reg(0, COP0_REG_Status);
257248
eie &= 0x10000;
258249

259250
if (eie)
@@ -278,8 +269,7 @@ void InvalidDCache(void *start, void *end)
278269
{
279270
int eie;
280271

281-
__asm__ __volatile__("mfc0\t%0, $12"
282-
: "=r"(eie));
272+
eie = get_mips_cop_reg(0, COP0_REG_Status);
283273
eie &= 0x10000;
284274

285275
if (eie)

‎ee/kernel/src/timer.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include <kernel.h>
1717
#include <timer.h>
1818
#include <string.h>
19+
#include <mipscopaccess.h>
1920

2021
#define TIMER_MODE_START 0x00000001
2122
#define TIMER_MODE_HANDLER 0x00000002
@@ -956,8 +957,7 @@ u32 cpu_ticks(void)
956957
{
957958
u32 out;
958959

959-
__asm__ __volatile__("mfc0\t%0, $9\n"
960-
: "=r"(out));
960+
out = get_mips_cop_reg(0, COP0_REG_Count);
961961
return out;
962962
}
963963
#endif

‎ee/kernel/src/tlbfunc.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ static int InitTLB32MB(void)
149149

150150
kprintf("# TLB spad=0 kernel=1:%d default=%d:%d extended=%d:%d\n", TLBInfo.NumKernelTLBEntries - 1, TLBInfo.NumKernelTLBEntries, TLBInfo.NumKernelTLBEntries + TLBInfo.NumDefaultTLBEntries - 1, TLBInfo.NumKernelTLBEntries + TLBInfo.NumDefaultTLBEntries, TLBInfo.NumKernelTLBEntries + TLBInfo.NumDefaultTLBEntries + TLBInfo.NumExtendedTLBEntries - 1);
151151

152-
__asm__ __volatile__("mtc0 $zero, $6\n");
152+
set_mips_cop_reg(0, COP0_REG_Wired, 0);
153153
EE_SYNCP();
154154

155155
if (TLBInfo.NumKernelTLBEntries >= 0x31) {
@@ -171,8 +171,7 @@ static int InitTLB32MB(void)
171171
}
172172

173173
TLBInfo.NumWiredEntries = NumTlbEntries = i;
174-
__asm__ __volatile__("mtc0 %0, $6\n"
175-
::"r"(NumTlbEntries));
174+
set_mips_cop_reg(0, COP0_REG_Wired, NumTlbEntries);
176175
EE_SYNCP();
177176

178177
if (TLBInfo.NumExtendedTLBEntries > 0) {

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