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Commit f899cbf

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author
Yvan Tortorella
committed
Add AXI error slave to network interface.
1 parent b139479 commit f899cbf

2 files changed

Lines changed: 59 additions & 37 deletions

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‎hw/floo_axi_chimney.sv‎

Lines changed: 35 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ module floo_axi_chimney #(
9898
// Duplicate AXI port signals to degenerate ports
9999
// in case they are not used
100100
axi_req_t axi_req_in;
101-
axi_rsp_t axi_rsp_out;
101+
axi_rsp_t axi_rsp_out, axi_in_rsp_err;
102102

103103
// AX queue
104104
axi_aw_chan_t axi_aw_queue;
@@ -158,14 +158,29 @@ module floo_axi_chimney #(
158158
meta_buf_t aw_out_hdr_in, aw_out_hdr_out;
159159
meta_buf_t ar_out_hdr_in, ar_out_hdr_out;
160160

161+
// Error signals from AR/AW address decoders
162+
logic [NumAxiChannels-1:0] decode_error_d, decode_error_q;
161163
///////////////////////
162164
// Spill registers //
163165
///////////////////////
164166

165167
if (ChimneyCfg.EnMgrPort) begin : gen_sbr_port
166168

167169
assign axi_req_in = axi_in_req_i;
168-
assign axi_in_rsp_o = axi_rsp_out;
170+
assign axi_in_rsp_o = (decode_error_q[AxiAr] || decode_error_q[AxiAw]) ? axi_in_rsp_err : axi_rsp_out;
171+
172+
axi_err_slv #(
173+
.AxiIdWidth ( AxiCfg.InIdWidth ),
174+
.ATOPs ( AtopSupport ),
175+
.axi_req_t ( axi_in_req_t ),
176+
.axi_resp_t ( axi_in_rsp_t )
177+
) i_axi_err_slv (
178+
.clk_i ( clk_i ),
179+
.rst_ni ( rst_ni ),
180+
.test_i ( test_enable_i ),
181+
.slv_req_i ( axi_in_req_i ),
182+
.slv_resp_o ( axi_in_rsp_err )
183+
);
169184

170185
if (ChimneyCfg.CutAx) begin : gen_ax_cuts
171186
spill_register #(
@@ -193,6 +208,9 @@ module floo_axi_chimney #(
193208
.valid_o ( axi_ar_queue_valid_out ),
194209
.ready_i ( axi_ar_queue_ready_in )
195210
);
211+
212+
`FF(decode_error_q[AxiAr], decode_error_d[AxiAr], '0)
213+
`FF(decode_error_q[AxiAw], decode_error_d[AxiAw], '0)
196214
end else begin : gen_no_ax_cuts
197215
assign axi_aw_queue = axi_in_req_i.aw;
198216
assign axi_aw_queue_valid_out = axi_in_req_i.aw_valid;
@@ -201,6 +219,9 @@ module floo_axi_chimney #(
201219
assign axi_ar_queue = axi_in_req_i.ar;
202220
assign axi_ar_queue_valid_out = axi_in_req_i.ar_valid;
203221
assign axi_rsp_out.ar_ready = axi_ar_queue_ready_in;
222+
223+
assign decode_error_q[AxiAr] = decode_error_d[AxiAr];
224+
assign decode_error_q[AxiAw] = decode_error_d[AxiAw];
204225
end
205226
end else begin : gen_err_slv_port
206227
axi_err_slv #(
@@ -398,11 +419,12 @@ module floo_axi_chimney #(
398419
.clk_i,
399420
.rst_ni,
400421
.route_table_i,
401-
.addr_map_i ( Sam ),
402-
.id_i ( id_t'('0) ),
403-
.addr_i ( axi_req_addr[ch] ),
404-
.route_o ( route_out[ch] ),
405-
.id_o ( id_out[ch] )
422+
.addr_map_i ( Sam ),
423+
.id_i ( id_t'('0) ),
424+
.addr_i ( axi_req_addr[ch] ),
425+
.route_o ( route_out[ch] ),
426+
.id_o ( id_out[ch] ),
427+
.decode_error_o ( decode_error_d[ch] )
406428
);
407429
end else if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting &&
408430
(Ch == AxiB || Ch == AxiR)) begin : gen_rsp_route_comp
@@ -420,11 +442,12 @@ module floo_axi_chimney #(
420442
.clk_i,
421443
.rst_ni,
422444
.route_table_i,
423-
.addr_i ( '0 ),
424-
.addr_map_i ( '0 ),
425-
.id_i ( axi_rsp_src_id[ch] ),
426-
.route_o ( route_out[ch] ),
427-
.id_o ( id_out[ch] )
445+
.addr_i ( '0 ),
446+
.addr_map_i ( Sam ),
447+
.id_i ( axi_rsp_src_id[ch] ),
448+
.route_o ( route_out[ch] ),
449+
.id_o ( id_out[ch] ),
450+
.decode_error_o ( decode_error_d[ch] )
428451
);
429452
end
430453
end

‎hw/floo_route_comp.sv‎

Lines changed: 24 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,8 @@ module floo_route_comp
2727
input addr_rule_t [RouteCfg.NumSamRules-1:0] addr_map_i,
2828
input route_t [RouteCfg.NumRoutes-1:0] route_table_i,
2929
output route_t route_o,
30-
output id_t id_o
30+
output id_t id_o,
31+
output logic decode_error_o
3132
);
3233

3334
// Use an address decoder to map the address to a destination ID.
@@ -36,42 +37,40 @@ module floo_route_comp
3637
// Further, the `rule_t` requires an additional field `id`, which can be used for the return route.
3738
// The reason for that is that a request destination is given by a physical address, while the
3839
// response destination is given by the ID of the source.
40+
41+
id_t addr_decode_id;
42+
43+
addr_decode #(
44+
.NoIndices ( RouteCfg.NumRoutes ),
45+
.NoRules ( RouteCfg.NumSamRules ),
46+
.addr_t ( addr_t ),
47+
.rule_t ( addr_rule_t ),
48+
.idx_t ( id_t )
49+
) i_addr_dst_decode (
50+
.addr_i ( addr_i ),
51+
.addr_map_i ( addr_map_i ),
52+
.idx_o ( addr_decode_id ),
53+
.dec_valid_o ( ),
54+
.dec_error_o ( decode_error_o ),
55+
.en_default_idx_i ( 1'b0 ),
56+
.default_idx_i ( '0 )
57+
);
58+
3959
if (UseIdTable &&
4060
((RouteCfg.RouteAlgo == IdTable) ||
4161
(RouteCfg.RouteAlgo == XYRouting) ||
4262
(RouteCfg.RouteAlgo == SourceRouting)))
4363
begin : gen_table_routing
44-
logic dec_error;
45-
46-
// This is simply to pass the assertions in addr_decode
47-
// It is not used otherwise, since we specify `idx_t`
48-
localparam int unsigned MaxPossibleId = 1 << $bits(id_o);
49-
50-
addr_decode #(
51-
.NoIndices ( MaxPossibleId ),
52-
.NoRules ( RouteCfg.NumSamRules ),
53-
.addr_t ( addr_t ),
54-
.rule_t ( addr_rule_t ),
55-
.idx_t ( id_t )
56-
) i_addr_dst_decode (
57-
.addr_i ( addr_i ),
58-
.addr_map_i ( addr_map_i ),
59-
.idx_o ( id_o ),
60-
.dec_valid_o ( ),
61-
.dec_error_o ( dec_error ),
62-
.en_default_idx_i ( 1'b0 ),
63-
.default_idx_i ( '0 )
64-
);
65-
66-
`ASSERT(DecodeError, !dec_error)
64+
assign id_o = addr_decode_id;
6765
end else if (RouteCfg.RouteAlgo == XYRouting) begin : gen_xy_bits_routing
6866
assign id_o.port_id = '0;
6967
assign id_o.x = addr_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)];
7068
assign id_o.y = addr_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)];
7169
end else if (RouteCfg.RouteAlgo == IdTable) begin : gen_id_bits_routing
7270
assign id_o = addr_i[RouteCfg.IdAddrOffset +: $bits(id_o)];
7371
end else if (RouteCfg.RouteAlgo == SourceRouting) begin : gen_source_routing
74-
// Nothing to do here
72+
// Default the ID output to 0
73+
assign id_o = '0;
7574
end else begin : gen_error
7675
$fatal(1, "Routing algorithm not implemented");
7776
end

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