Bump ACE repository to latest version

Bender.yml

@@ -1,38 +1,63 @@
 package:
   name: ace
+  # Authors in alphabetical order (surname)
   authors:
-    # Alphabetically ordered by last name (maintainers first)
+    - "Aleksi Korsman <aleksi.korsman@aalto.fi>"
+    - "Riccardo Tedeschi <riccardo.tedeschi6@unibo.it>"
 
 dependencies:
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.2 }
+  axi:               { git: "https://github.com/pulp-platform/axi.git",               version: 0.39.9 }
+  common_cells:      { git: "https://github.com/pulp-platform/common_cells.git",      version: 1.39.0 }
+  axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", rev: 6d3c8b4    } # branch: master
+  apb:               { git: "https://github.com/pulp-platform/apb.git",               version: 0.2.4  }
 
 export_include_dirs:
   - include
 
 sources:
-  # Source files grouped in levels. Files in level 0 have no dependencies on files in this
-  # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
-  # levels 1 and 0, etc. Files within a level are ordered alphabetically.
-  # Level 0
+  # Generic ACE package and interfaces
   - src/ace_pkg.sv
-  - src/snoop_pkg.sv
-  # Level 1
   - src/ace_intf.sv
   - src/snoop_intf.sv
-  # Level 2
-  - src/ace_trs_dec.sv
-  - src/ccu_fsm.sv
-  # Level 3
-  - src/ace_ccu_top.sv
+  # CCU package
+  - src/ccu/ccu_pkg.sv
+    # CCU generated regs
+  - src/ccu/regs/generated/ccu_csr_pkg.sv
+  - src/ccu/regs/generated/ccu_csr.sv
+  # CCU source files
+  - src/ccu/ccu_csr_wrap.sv
+  - src/ccu/ccu_exclusive_monitor.sv
+  - src/ccu/ccu_frontend_arbiter.sv
+  - src/ccu/ccu_frontend.sv
+  - src/ccu/ccu_read_engine.sv
+  - src/ccu/ccu_replay.sv
+  - src/ccu/ccu_scoreboard.sv
+  - src/ccu/ccu_snoop_pipeline.sv
+  - src/ccu/ccu_top.sv
+  - src/ccu/ccu_write_engine.sv
 
-  - target: simulation
-    files:
-      - src/ace_test.sv
-      - src/snoop_test.sv
+  #- target: simulation
+  #  files:
+  #    - src/ace_test.sv
+  #    - src/snoop_test.sv
 
-  - target: test
-    files:
-      # Level 0
-      - test/tb_ace_ccu_pkg.sv
-      # Level 1
-      - test/tb_ace_ccu_top.sv
+  #- target: test
+  #  files:
+  #    # Level 0
+  #    - test/tb_ace_ccu_pkg.sv
+  #    # Level 1
+  #    - test/tb_ace_ccu_top.sv
+
+  #- target: vscode
+  #  files:
+  #    - src/ccu/ccu_ctrl_wr_snoop.sv
+
+  # - target: test
+  #   files:
+  #     # Level 0
+  #     - test/vip/ace_test_pkg.sv
+  #     - test/vip/snoop_test_pkg.sv
+  #     # Level 1
+  #     - test/vip/cache_test_pkg.sv
+  #     # Level 2
+  #     - test/tb_ace_ccu_top.sv

Makefile

@@ -24,6 +24,44 @@ TBS         ?= ace_ccu_top \
 
 SIM_TARGETS := $(addsuffix .log,$(addprefix sim-,$(TBS)))
 
+####### Simulation parameters #######
+# Address width
+ADDR_WIDTH 			?= 32
+# AXI/ACE data width
+DATA_WIDTH 			?= 64
+# Cache line word width
+WORD_WIDTH 			?= 64
+# Number of words in a cache line
+CACHELINE_WORDS ?= 4
+# Number of ways in the cache model
+WAYS 						?= 2
+# Number of sets in the cache model
+SETS 						?= 16
+# Number of cached masters
+NMASTERS 				?= 4
+# Number of master groups
+NGROUPS 				?= 2
+# Number of transactions to be generated per master
+NTRANSACTIONS 	?= 100
+# Location of the generated files
+MEM_DIR 				?= $(PWD)/build/mem
+# Seed for initial state generation. If empty, no seed
+SEED						?= 10
+# Run coherency check after simulation
+CHECK 					?= 0
+# Debug mode for coherency checking
+DEBUG 					?= 1
+
+export ADDR_WIDTH
+export DATA_WIDTH
+export WORD_WIDTH
+export CACHELINE_WORDS
+export WAYS
+export SETS
+export NMASTERS
+export NGROUPS
+export NTRANSACTIONS
+export MEM_DIR
 
 .SHELL: bash
 
@@ -51,6 +89,24 @@ sim_all: $(SIM_TARGETS)
 build:
 	mkdir -p $@
 
+build/mem: build
+	mkdir -p $@
+
+init_mem: build/mem
+	python3 test/vip/python/cache_coherency_test.py \
+	--addr_width ${ADDR_WIDTH} \
+	--data_width ${DATA_WIDTH} \
+	--word_width ${WORD_WIDTH} \
+	--cacheline_words ${CACHELINE_WORDS} \
+	--ways ${WAYS} \
+	--sets ${SETS} \
+	--n_caches ${NMASTERS} \
+	--n_transactions ${NTRANSACTIONS} \
+	--target_dir $(MEM_DIR) \
+	--seed $(SEED) \
+	$(if $(filter 1, $(CHECK)),--check) \
+	$(if $(filter 1, $(DEBUG)),--debug)
+
 
 elab.log: Bender.yml | build
 	export SYNOPSYS_DC="$(SYNOPSYS_DC)"; cd build && ../scripts/synth.sh | tee ../$@

README.md

@@ -1,13 +1,64 @@
 # ACE SystemVerilog modules for cache coherent SoC design
 
-This repository provides modules to implement cache coherence SoC's.
+> 🚧 **Work in progress:** this repository is under active development. Breaking changes can happen at any time. 🚧
 
-## List of modules
+This repository provides modules to implement cache coherence SoCs.
 
-| Name                                                 | Description                                                                                                  | Doc                            |
-|------------------------------------------------------|--------------------------------------------------------------------------------------------------------------|--------------------------------|
-| [`ace_ccu_top`](src/ace_ccu_top.sv)                  | ACE interconnector, broadcasts snooping messages to the cache controllers and AXI transactions to the slave  | [Doc](doc/ace_ccu_top.md)      |
+## Repository structure
+
+```
+src/
+├── ace_intf.sv        # ACE bus interface definitions
+├── ace_pkg.sv         # ACE type definitions and constants
+├── snoop_intf.sv      # Snoop channel interface definitions
+└── ccu/               # Coherence Control Unit
+    ├── ccu_top.sv
+    ├── ccu_pkg.sv
+    ├── ccu_frontend.sv
+    ├── ccu_frontend_arbiter.sv
+    ├── ccu_read_engine.sv
+    ├── ccu_write_engine.sv
+    ├── ccu_snoop_pipeline.sv
+    ├── ccu_replay.sv
+    ├── ccu_exclusive_monitor.sv
+    ├── ccu_csr_wrap.sv
+    ├── ccu_scoreboard.sv
+    └── regs/          # CSR definitions and generated register files
+
+include/
+└── ace/               # SystemVerilog header files (typedef, assign, convert, domain macros)
+```
+
+## Include files
+
+| Name                                              | Description                                        |
+|---------------------------------------------------|----------------------------------------------------|
+| [`ace/typedef.svh`](include/ace/typedef.svh)      | Macros for defining ACE and snoop struct types     |
+| [`ace/assign.svh`](include/ace/assign.svh)        | Macros for assigning ACE and snoop signals         |
+| [`ace/convert.svh`](include/ace/convert.svh)      | Macros for converting between ACE signal formats   |
+| [`ace/domain.svh`](include/ace/domain.svh)        | Macros for ACE domain signal handling              |
 
 ## License
 
-The ACE repository is released under Solderpad v0.51 (SHL-0.51) see [LICENSE](LICENSE)
+The ACE repository is released under Solderpad v0.51 (SHL-0.51) see [LICENSE](LICENSE)
+
+## Publication
+
+If you use ACE/Culsans in your work, you can cite us:
+
+```
+@article{tedeschi2024culsans,
+    title={Culsans: An Efficient Snoop-based Coherency Unit
+           for the CVA6 Open Source RISC-V application processor},
+    volume={10},
+    number={2},
+    journal={WiPiEC Journal - Works in Progress in Embedded Computing Journal},
+    author={Tedeschi, Riccardo and Valente, Luca and Ottavi, Gianmarco and
+            Zelioli, Enrico and Wistoff, Nils and
+            Giacometti, Massimiliano and Basit Sajjad, Abdul and
+            Benini, Luca and Rossi, Davide},
+    year={2024},
+    month={Aug.}
+}
+
+```

include/ace/assign.svh

@@ -17,6 +17,7 @@
 `define ACE_ASSIGN_SVH_
 
 `include "axi/assign.svh"
+`include "ace/assign.svh"
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 // Internal implementation for assigning one ACE struct or interface to another struct or interface.
@@ -71,9 +72,7 @@
   __opt_as __lhs.b_ready = __rhs.b_ready;                           \
   `__ACE_TO_AR(__opt_as, __lhs.ar, __lhs_sep, __rhs.ar, __rhs_sep)  \
   __opt_as __lhs.ar_valid = __rhs.ar_valid;                         \
-  __opt_as __lhs.r_ready = __rhs.r_ready;                           \
-  __opt_as __lhs.wack = __rhs.wack;                                 \
-  __opt_as __lhs.rack = __rhs.rack;
+  __opt_as __lhs.r_ready = __rhs.r_ready;
 `define __ACE_TO_RESP(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \
   __opt_as __lhs.aw_ready = __rhs.aw_ready;                         \
   __opt_as __lhs.ar_ready = __rhs.ar_ready;                         \
@@ -116,9 +115,7 @@
   `AXI_ASSIGN_W(slv, mst)     \
   `AXI_ASSIGN_B(mst, slv)     \
   `ACE_ASSIGN_AR(slv, mst)    \
-  `ACE_ASSIGN_R(mst, slv)     \
-  assign slv.wack = mst.wack; \
-  assign slv.rack = mst.rack;
+  `ACE_ASSIGN_R(mst, slv)
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -146,9 +143,7 @@
   assign mon_dv.ar_ready  = axi_if.ar_ready;        \
   `__ACE_TO_R(assign, mon_dv.r, _, axi_if.r, _)     \
   assign mon_dv.r_valid   = axi_if.r_valid;         \
-  assign mon_dv.r_ready   = axi_if.r_ready;         \
-  assign mon_dv.wack   = axi_if.wack;               \
-  assign mon_dv.rack   = axi_if.rack;
+  assign mon_dv.r_ready   = axi_if.r_ready;
 ////////////////////////////////////////////////////////////////////////////////////////////////////
 
 
@@ -317,7 +312,7 @@
   __opt_as __lhs.cd_valid = __rhs.cd_valid;                               \
   `__SNOOP_TO_CD(__opt_as, __lhs.cd, __lhs_sep, __rhs.cd, __rhs_sep)      \
   __opt_as __lhs.cr_valid = __rhs.cr_valid;                               \
-  __opt_as __lhs.cr_resp = __rhs.cr_resp;
+  __opt_as __lhs.cr = __rhs.cr;
 ////////////////////////////////////////////////////////////////////////////////////////////////////