Skip to content

Commit 55650af

Browse files
ricted98Yvan Tortorella
ricted98
and
Yvan Tortorella
authored
fix(fpga): implement VCU128 DRAM controller without ECC correction (#272)
* fix(fpga): Remove ECC on VCU128's DDR4 * fix(fpga): cleanup unneeded control port in DRAM wrapper --------- Co-authored-by: Yvan Tortorella <ytortorella@lagrev5.ee.ethz.ch>
1 parent 2d40a3b commit 55650af

5 files changed

Lines changed: 360 additions & 28 deletions

File tree

‎target/xilinx/constraints/vcu128.xdc‎

Lines changed: 350 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,4 +83,354 @@ set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n]
8383
set_property PACKAGE_PIN BM29 [get_ports sys_reset]
8484
set_property IOSTANDARD LVCMOS12 [get_ports sys_reset]
8585

86+
# MIG interface
87+
set_property PACKAGE_PIN BF50 [get_ports "c0_ddr4_adr[0]"]
88+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[0]"]
89+
90+
set_property PACKAGE_PIN BD51 [get_ports "c0_ddr4_adr[1]"]
91+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[1]"]
92+
93+
set_property PACKAGE_PIN BG48 [get_ports "c0_ddr4_adr[2]"]
94+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[2]"]
95+
96+
set_property PACKAGE_PIN BE50 [get_ports "c0_ddr4_adr[3]"]
97+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[3]"]
98+
99+
set_property PACKAGE_PIN BE49 [get_ports "c0_ddr4_adr[4]"]
100+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[4]"]
101+
102+
set_property PACKAGE_PIN BE51 [get_ports "c0_ddr4_adr[5]"]
103+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[5]"]
104+
105+
set_property PACKAGE_PIN BF53 [get_ports "c0_ddr4_adr[6]"]
106+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[6]"]
107+
108+
set_property PACKAGE_PIN BG50 [get_ports "c0_ddr4_adr[7]"]
109+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[7]"]
110+
111+
set_property PACKAGE_PIN BF51 [get_ports "c0_ddr4_adr[8]"]
112+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[8]"]
113+
114+
set_property PACKAGE_PIN BG47 [get_ports "c0_ddr4_adr[9]"]
115+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[9]"]
116+
117+
set_property PACKAGE_PIN BF47 [get_ports "c0_ddr4_adr[10]"]
118+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[10]"]
119+
120+
set_property PACKAGE_PIN BG49 [get_ports "c0_ddr4_adr[11]"]
121+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[11]"]
122+
123+
set_property PACKAGE_PIN BF48 [get_ports "c0_ddr4_adr[12]"]
124+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[12]"]
125+
126+
set_property PACKAGE_PIN BF52 [get_ports "c0_ddr4_adr[13]"]
127+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[13]"]
128+
129+
set_property PACKAGE_PIN BG53 [get_ports "c0_ddr4_adr[14]"]
130+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[14]"]
131+
132+
set_property PACKAGE_PIN BH54 [get_ports "c0_ddr4_adr[15]"]
133+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[15]"]
134+
135+
set_property PACKAGE_PIN BJ54 [get_ports "c0_ddr4_adr[16]"]
136+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_adr[16]"]
137+
138+
set_property PACKAGE_PIN BE54 [get_ports "c0_ddr4_ba[0]"]
139+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_ba[0]"]
140+
141+
set_property PACKAGE_PIN BE53 [get_ports "c0_ddr4_ba[1]"]
142+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_ba[1]"]
143+
144+
set_property PACKAGE_PIN BG54 [get_ports "c0_ddr4_bg[0]"]
145+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
146+
147+
set_property PACKAGE_PIN BK54 [get_ports "c0_ddr4_ck_c[0]"]
148+
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_ddr4_ck_c[0]"]
149+
150+
set_property PACKAGE_PIN BK53 [get_ports "c0_ddr4_ck_t[0]"]
151+
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_ddr4_ck_t[0]"]
152+
153+
set_property PACKAGE_PIN BH52 [get_ports "c0_ddr4_cke[0]"]
154+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_cke[0]"]
155+
156+
set_property PACKAGE_PIN BG52 [get_ports "c0_ddr4_act_n"]
157+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_act_n"]
158+
159+
set_property PACKAGE_PIN BH50 [get_ports "c0_ddr4_reset_n"]
160+
set_property IOSTANDARD LVCMOS12 [get_ports "c0_ddr4_reset_n"]
161+
162+
set_property PACKAGE_PIN BH49 [get_ports "c0_ddr4_odt[0]"]
163+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_odt[0]"]
164+
165+
set_property PACKAGE_PIN BK48 [get_ports "c0_ddr4_cs_n[1]"]
166+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_cs_n[1]"]
167+
168+
set_property PACKAGE_PIN BP49 [get_ports "c0_ddr4_cs_n[0]"]
169+
set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_cs_n[0]"]
170+
171+
set_property PACKAGE_PIN BM45 [get_ports "c0_ddr4_dq[0]"]
172+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[0]"]
173+
174+
set_property PACKAGE_PIN BP44 [get_ports "c0_ddr4_dq[1]"]
175+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[1]"]
176+
177+
set_property PACKAGE_PIN BP47 [get_ports "c0_ddr4_dq[2]"]
178+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[2]"]
179+
180+
set_property PACKAGE_PIN BN45 [get_ports "c0_ddr4_dq[3]"]
181+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[3]"]
182+
183+
set_property PACKAGE_PIN BM44 [get_ports "c0_ddr4_dq[4]"]
184+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[4]"]
185+
186+
set_property PACKAGE_PIN BN44 [get_ports "c0_ddr4_dq[5]"]
187+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[5]"]
188+
189+
set_property PACKAGE_PIN BN47 [get_ports "c0_ddr4_dq[6]"]
190+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[6]"]
191+
192+
set_property PACKAGE_PIN BP43 [get_ports "c0_ddr4_dq[7]"]
193+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[7]"]
194+
195+
set_property PACKAGE_PIN BL45 [get_ports "c0_ddr4_dq[8]"]
196+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[8]"]
197+
198+
set_property PACKAGE_PIN BK44 [get_ports "c0_ddr4_dq[9]"]
199+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[9]"]
200+
201+
set_property PACKAGE_PIN BL46 [get_ports "c0_ddr4_dq[10]"]
202+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[10]"]
203+
204+
set_property PACKAGE_PIN BK43 [get_ports "c0_ddr4_dq[11]"]
205+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[11]"]
206+
207+
set_property PACKAGE_PIN BL43 [get_ports "c0_ddr4_dq[12]"]
208+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[12]"]
209+
210+
set_property PACKAGE_PIN BJ44 [get_ports "c0_ddr4_dq[13]"]
211+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[13]"]
212+
213+
set_property PACKAGE_PIN BL42 [get_ports "c0_ddr4_dq[14]"]
214+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[14]"]
215+
216+
set_property PACKAGE_PIN BJ43 [get_ports "c0_ddr4_dq[15]"]
217+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[15]"]
218+
219+
set_property PACKAGE_PIN BK41 [get_ports "c0_ddr4_dq[16]"]
220+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[16]"]
221+
222+
set_property PACKAGE_PIN BG44 [get_ports "c0_ddr4_dq[17]"]
223+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[17]"]
224+
225+
set_property PACKAGE_PIN BG42 [get_ports "c0_ddr4_dq[18]"]
226+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[18]"]
227+
228+
set_property PACKAGE_PIN BH44 [get_ports "c0_ddr4_dq[19]"]
229+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[19]"]
230+
231+
set_property PACKAGE_PIN BH45 [get_ports "c0_ddr4_dq[20]"]
232+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[20]"]
233+
234+
set_property PACKAGE_PIN BG45 [get_ports "c0_ddr4_dq[21]"]
235+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[21]"]
236+
237+
set_property PACKAGE_PIN BG43 [get_ports "c0_ddr4_dq[22]"]
238+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[22]"]
239+
240+
set_property PACKAGE_PIN BJ41 [get_ports "c0_ddr4_dq[23]"]
241+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[23]"]
242+
243+
set_property PACKAGE_PIN BE43 [get_ports "c0_ddr4_dq[24]"]
244+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[24]"]
245+
246+
set_property PACKAGE_PIN BF42 [get_ports "c0_ddr4_dq[25]"]
247+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[25]"]
248+
249+
set_property PACKAGE_PIN BC42 [get_ports "c0_ddr4_dq[26]"]
250+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[26]"]
251+
252+
set_property PACKAGE_PIN BF43 [get_ports "c0_ddr4_dq[27]"]
253+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[27]"]
254+
255+
set_property PACKAGE_PIN BD42 [get_ports "c0_ddr4_dq[28]"]
256+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[28]"]
257+
258+
set_property PACKAGE_PIN BF45 [get_ports "c0_ddr4_dq[29]"]
259+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[29]"]
260+
261+
set_property PACKAGE_PIN BE44 [get_ports "c0_ddr4_dq[30]"]
262+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[30]"]
263+
264+
set_property PACKAGE_PIN BF46 [get_ports "c0_ddr4_dq[31]"]
265+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[31]"]
266+
267+
set_property PACKAGE_PIN BP32 [get_ports "c0_ddr4_dq[32]"]
268+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[32]"]
269+
270+
set_property PACKAGE_PIN BP29 [get_ports "c0_ddr4_dq[33]"]
271+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[33]"]
272+
273+
set_property PACKAGE_PIN BP31 [get_ports "c0_ddr4_dq[34]"]
274+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[34]"]
275+
276+
set_property PACKAGE_PIN BP28 [get_ports "c0_ddr4_dq[35]"]
277+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[35]"]
278+
279+
set_property PACKAGE_PIN BN32 [get_ports "c0_ddr4_dq[36]"]
280+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[36]"]
281+
282+
set_property PACKAGE_PIN BM30 [get_ports "c0_ddr4_dq[37]"]
283+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[37]"]
284+
285+
set_property PACKAGE_PIN BN31 [get_ports "c0_ddr4_dq[38]"]
286+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[38]"]
287+
288+
set_property PACKAGE_PIN BL30 [get_ports "c0_ddr4_dq[39]"]
289+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[39]"]
290+
291+
set_property PACKAGE_PIN BL32 [get_ports "c0_ddr4_dq[40]"]
292+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[40]"]
293+
294+
set_property PACKAGE_PIN BP34 [get_ports "c0_ddr4_dq[41]"]
295+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[41]"]
296+
297+
set_property PACKAGE_PIN BN34 [get_ports "c0_ddr4_dq[42]"]
298+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[42]"]
299+
300+
set_property PACKAGE_PIN BK33 [get_ports "c0_ddr4_dq[43]"]
301+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[43]"]
302+
303+
set_property PACKAGE_PIN BL31 [get_ports "c0_ddr4_dq[44]"]
304+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[44]"]
305+
306+
set_property PACKAGE_PIN BL33 [get_ports "c0_ddr4_dq[45]"]
307+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[45]"]
308+
309+
set_property PACKAGE_PIN BM33 [get_ports "c0_ddr4_dq[46]"]
310+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[46]"]
311+
312+
set_property PACKAGE_PIN BK31 [get_ports "c0_ddr4_dq[47]"]
313+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[47]"]
314+
315+
set_property PACKAGE_PIN BJ34 [get_ports "c0_ddr4_dq[48]"]
316+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[48]"]
317+
318+
set_property PACKAGE_PIN BG35 [get_ports "c0_ddr4_dq[49]"]
319+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[49]"]
320+
321+
set_property PACKAGE_PIN BH34 [get_ports "c0_ddr4_dq[50]"]
322+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[50]"]
323+
324+
set_property PACKAGE_PIN BH35 [get_ports "c0_ddr4_dq[51]"]
325+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[51]"]
326+
327+
set_property PACKAGE_PIN BJ33 [get_ports "c0_ddr4_dq[52]"]
328+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[52]"]
329+
330+
set_property PACKAGE_PIN BF35 [get_ports "c0_ddr4_dq[53]"]
331+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[53]"]
332+
333+
set_property PACKAGE_PIN BG34 [get_ports "c0_ddr4_dq[54]"]
334+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[54]"]
335+
336+
set_property PACKAGE_PIN BF36 [get_ports "c0_ddr4_dq[55]"]
337+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[55]"]
338+
339+
set_property PACKAGE_PIN BF31 [get_ports "c0_ddr4_dq[56]"]
340+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[56]"]
341+
342+
set_property PACKAGE_PIN BH30 [get_ports "c0_ddr4_dq[57]"]
343+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[57]"]
344+
345+
set_property PACKAGE_PIN BJ31 [get_ports "c0_ddr4_dq[58]"]
346+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[58]"]
347+
348+
set_property PACKAGE_PIN BG32 [get_ports "c0_ddr4_dq[59]"]
349+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[59]"]
350+
351+
set_property PACKAGE_PIN BH31 [get_ports "c0_ddr4_dq[60]"]
352+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[60]"]
353+
354+
set_property PACKAGE_PIN BF32 [get_ports "c0_ddr4_dq[61]"]
355+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[61]"]
356+
357+
set_property PACKAGE_PIN BH29 [get_ports "c0_ddr4_dq[62]"]
358+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[62]"]
359+
360+
set_property PACKAGE_PIN BF33 [get_ports "c0_ddr4_dq[63]"]
361+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dq[63]"]
362+
363+
set_property PACKAGE_PIN BK30 [get_ports "c0_ddr4_dqs_c[7]"]
364+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[7]"]
365+
366+
set_property PACKAGE_PIN BK35 [get_ports "c0_ddr4_dqs_c[6]"]
367+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[6]"]
368+
369+
set_property PACKAGE_PIN BM35 [get_ports "c0_ddr4_dqs_c[5]"]
370+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[5]"]
371+
372+
set_property PACKAGE_PIN BN30 [get_ports "c0_ddr4_dqs_c[4]"]
373+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[4]"]
374+
375+
set_property PACKAGE_PIN BE46 [get_ports "c0_ddr4_dqs_c[3]"]
376+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[3]"]
377+
378+
set_property PACKAGE_PIN BJ46 [get_ports "c0_ddr4_dqs_c[2]"]
379+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[2]"]
380+
381+
set_property PACKAGE_PIN BK46 [get_ports "c0_ddr4_dqs_c[1]"]
382+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[1]"]
383+
384+
set_property PACKAGE_PIN BP46 [get_ports "c0_ddr4_dqs_c[0]"]
385+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_c[0]"]
386+
387+
set_property PACKAGE_PIN BJ29 [get_ports "c0_ddr4_dqs_t[7]"]
388+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[7]"]
389+
390+
set_property PACKAGE_PIN BK34 [get_ports "c0_ddr4_dqs_t[6]"]
391+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[6]"]
392+
393+
set_property PACKAGE_PIN BL35 [get_ports "c0_ddr4_dqs_t[5]"]
394+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[5]"]
395+
396+
set_property PACKAGE_PIN BN29 [get_ports "c0_ddr4_dqs_t[4]"]
397+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[4]"]
398+
399+
set_property PACKAGE_PIN BE45 [get_ports "c0_ddr4_dqs_t[3]"]
400+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[3]"]
401+
402+
set_property PACKAGE_PIN BH46 [get_ports "c0_ddr4_dqs_t[2]"]
403+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[2]"]
404+
405+
set_property PACKAGE_PIN BK45 [get_ports "c0_ddr4_dqs_t[1]"]
406+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[1]"]
407+
408+
set_property PACKAGE_PIN BN46 [get_ports "c0_ddr4_dqs_t[0]"]
409+
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "c0_ddr4_dqs_t[0]"]
410+
411+
set_property PACKAGE_PIN BG29 [get_ports "c0_ddr4_dm_dbi_n[7]"]
412+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[7]"]
413+
414+
set_property PACKAGE_PIN BH32 [get_ports "c0_ddr4_dm_dbi_n[6]"]
415+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[6]"]
416+
417+
set_property PACKAGE_PIN BM34 [get_ports "c0_ddr4_dm_dbi_n[5]"]
418+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[5]"]
419+
420+
set_property PACKAGE_PIN BM28 [get_ports "c0_ddr4_dm_dbi_n[4]"]
421+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[4]"]
422+
423+
set_property PACKAGE_PIN BD41 [get_ports "c0_ddr4_dm_dbi_n[3]"]
424+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[3]"]
425+
426+
set_property PACKAGE_PIN BH42 [get_ports "c0_ddr4_dm_dbi_n[2]"]
427+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[2]"]
428+
429+
set_property PACKAGE_PIN BL47 [get_ports "c0_ddr4_dm_dbi_n[1]"]
430+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[1]"]
431+
432+
set_property PACKAGE_PIN BN42 [get_ports "c0_ddr4_dm_dbi_n[0]"]
433+
set_property IOSTANDARD POD12_DCI [get_ports "c0_ddr4_dm_dbi_n[0]"]
434+
435+
86436
# tclint-enable line-length, spacing

‎target/xilinx/scripts/impl_ip.tcl‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -183,15 +183,15 @@ switch $proj {
183183
vcu128 {
184184
set_property -dict [list \
185185
CONFIG.C0.DDR4_Clamshell {true} \
186-
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \
186+
CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
187187
CONFIG.System_Clock {No_Buffer} \
188188
CONFIG.Reference_Clock {No_Buffer} \
189189
CONFIG.C0.DDR4_InputClockPeriod {10000} \
190190
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
191191
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
192-
CONFIG.C0.DDR4_DataWidth {72} \
193-
CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
194-
CONFIG.C0.DDR4_Ecc {true} \
192+
CONFIG.C0.DDR4_DataWidth {64} \
193+
CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
194+
CONFIG.C0.DDR4_Ecc {false} \
195195
CONFIG.C0.DDR4_AxiDataWidth {512} \
196196
CONFIG.C0.DDR4_AxiAddressWidth {32} \
197197
CONFIG.C0.DDR4_AxiIDWidth {8} \

‎target/xilinx/scripts/impl_sys.tcl‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,9 @@ import_files -fileset constrs_1 -norecurse ${xilinx_root}/constraints/${board}.x
2222
# Load RTL sources
2323
source ${xilinx_root}/scripts/add_sources.${board}.tcl
2424

25+
# Avoid changing top level randomly in case of error
26+
set_property source_mgmt_mode None [current_project]
27+
2528
# Set top module
2629
set_property top ${proj}_top_xilinx [current_fileset]
2730
update_compile_order -fileset sources_1

‎target/xilinx/src/cheshire_top_xilinx.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@
1717
module cheshire_top_xilinx import cheshire_pkg::*; #(
1818
`ifdef TARGET_VCU128
1919
localparam int unsigned Ddr4CsNWidth = 2,
20-
localparam int unsigned Ddr4DmDbiNWidth = 9,
21-
localparam int unsigned Ddr4DqWidth = 72,
22-
localparam int unsigned Ddr4DqsWidth = 9
20+
localparam int unsigned Ddr4DmDbiNWidth = 8,
21+
localparam int unsigned Ddr4DqWidth = 64,
22+
localparam int unsigned Ddr4DqsWidth = 8
2323
`else // Default to VCU118
2424
localparam int unsigned Ddr4CsNWidth = 1,
2525
localparam int unsigned Ddr4DmDbiNWidth = 8,

0 commit comments

Comments
 (0)