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Merge pull request #10 from pulp-platform/michaero/rename_set_to_way
Rename SET_COUNT to WAY_COUNT
2 parents 73f4f02 + d6d6fa5 commit 27fe3ee

8 files changed

Lines changed: 42 additions & 39 deletions

‎Changelog.md‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
99
### Fixed
1010
- lookup_serial: Make `write_ready_o` independent of `write_valid_i`.
1111

12+
### Changed
13+
- Rename `SET_COUNT` to `WAY_COUNT` to correct terminology, as it reflects the number of ways in a set.
14+
1215
## 0.1.1 - 28.06.2024
1316
### Added
1417
- Allow fetches to bypass prefetches in L1.

‎src/snitch_icache.sv‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,14 +10,14 @@
1010
module snitch_icache #(
1111
/// Number of request (fetch) ports
1212
parameter int unsigned NR_FETCH_PORTS = -1,
13-
/// L0 Cache Line Count
13+
/// L0 Cache Line Count (L0 is fully associative)
1414
parameter int unsigned L0_LINE_COUNT = -1,
1515
/// Cache Line Width
1616
parameter int unsigned LINE_WIDTH = -1,
1717
/// The number of cache lines per set. Power of two; >= 2.
1818
parameter int unsigned LINE_COUNT = -1,
1919
/// The set associativity of the cache. Power of two; >= 1.
20-
parameter int unsigned SET_COUNT = 1,
20+
parameter int unsigned WAY_COUNT = 1,
2121
/// Fetch interface address width. Same as FILL_AW; >= 1.
2222
parameter int unsigned FETCH_AW = -1,
2323
/// Fetch interface data width. Power of two; >= 8.
@@ -88,7 +88,7 @@ module snitch_icache #(
8888
LINE_WIDTH: LINE_WIDTH,
8989
LINE_COUNT: LINE_COUNT,
9090
L0_LINE_COUNT: L0_LINE_COUNT,
91-
SET_COUNT: SET_COUNT,
91+
WAY_COUNT: WAY_COUNT,
9292
PENDING_COUNT: NUM_AXI_OUTSTANDING,
9393
FETCH_AW: FETCH_AW,
9494
FETCH_DW: FETCH_DW,
@@ -103,7 +103,7 @@ module snitch_icache #(
103103
FILL_ALIGN: $clog2(FILL_DW/8),
104104
LINE_ALIGN: $clog2(LINE_WIDTH/8),
105105
COUNT_ALIGN: $clog2(LINE_COUNT),
106-
SET_ALIGN: $clog2(SET_COUNT),
106+
SET_ALIGN: $clog2(WAY_COUNT),
107107
TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8) - $clog2(LINE_COUNT),
108108
L0_TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8),
109109
L0_EARLY_TAG_WIDTH:
@@ -119,7 +119,7 @@ module snitch_icache #(
119119
assert(L0_LINE_COUNT > 0);
120120
assert(LINE_WIDTH > 0);
121121
assert(LINE_COUNT > 1);
122-
assert(SET_COUNT >= 2) else $warning("Only >= 2 sets are supported");
122+
assert(WAY_COUNT >= 2) else $warning("Only >= 2 sets are supported");
123123
assert(FETCH_AW > 0);
124124
assert(FETCH_DW > 0);
125125
assert(FILL_AW > 0);
@@ -131,7 +131,7 @@ module snitch_icache #(
131131
assert(2**$clog2(LINE_COUNT) == LINE_COUNT)
132132
else $fatal(1, "Cache LINE_COUNT %0d is not a power of two", LINE_COUNT);
133133
// NOTE(fschuiki): I think the following is not needed
134-
// assert(2**$clog2(SET_COUNT) == SET_COUNT) else $fatal(1, "Cache SET_COUNT %0d is not a power of two", SET_COUNT);
134+
// assert(2**$clog2(WAY_COUNT) == WAY_COUNT) else $fatal(1, "Cache WAY_COUNT %0d is not a power of two", WAY_COUNT);
135135
assert(2**$clog2(FETCH_DW) == FETCH_DW)
136136
else $fatal(1, "Cache FETCH_DW %0d is not a power of two", FETCH_DW);
137137
assert(2**$clog2(FILL_DW) == FILL_DW)

‎src/snitch_icache_lookup_parallel.sv‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,9 @@ module snitch_icache_lookup_parallel #(
5050
// Multiplex read and write access to the RAMs onto one port, prioritizing
5151
// write accesses.
5252
logic [CFG.COUNT_ALIGN-1:0] ram_addr ;
53-
logic [CFG.SET_COUNT-1:0] ram_enable ;
54-
logic [CFG.LINE_WIDTH-1:0] ram_wdata, ram_rdata [CFG.SET_COUNT] ;
55-
logic [CFG.TAG_WIDTH+1:0] ram_wtag, ram_rtag [CFG.SET_COUNT] ;
53+
logic [CFG.WAY_COUNT-1:0] ram_enable ;
54+
logic [CFG.LINE_WIDTH-1:0] ram_wdata, ram_rdata [CFG.WAY_COUNT] ;
55+
logic [CFG.TAG_WIDTH+1:0] ram_wtag, ram_rtag [CFG.WAY_COUNT] ;
5656
logic ram_write ;
5757
logic ram_write_q;
5858
logic [CFG.COUNT_ALIGN:0] init_count_q;
@@ -86,7 +86,7 @@ module snitch_icache_lookup_parallel #(
8686
ram_wtag = '0;
8787
end else if (write_valid_i) begin
8888
ram_addr = write_addr_i;
89-
ram_enable = CFG.SET_COUNT > 1 ? $unsigned(1 << write_set_i) : 1'b1;
89+
ram_enable = CFG.WAY_COUNT > 1 ? $unsigned(1 << write_set_i) : 1'b1;
9090
ram_write = 1'b1;
9191
write_ready_o = 1'b1;
9292
end else if (out_ready_i) begin
@@ -144,7 +144,7 @@ module snitch_icache_lookup_parallel #(
144144
end
145145

146146
// Instantiate the RAM sets.
147-
for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets
147+
for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : g_sets
148148
tc_sram_impl #(
149149
.NumWords (CFG.LINE_COUNT),
150150
.DataWidth (CFG.TAG_WIDTH+2),
@@ -188,12 +188,12 @@ module snitch_icache_lookup_parallel #(
188188

189189
// Determine which RAM line hit, and multiplex that data to the output.
190190
logic [CFG.TAG_WIDTH-1:0] required_tag;
191-
logic [CFG.SET_COUNT-1:0] line_hit;
191+
logic [CFG.WAY_COUNT-1:0] line_hit;
192192

193193
always_comb begin
194-
automatic logic [CFG.SET_COUNT-1:0] errors;
194+
automatic logic [CFG.WAY_COUNT-1:0] errors;
195195
required_tag = addr_q[CFG.FETCH_AW-1:CFG.LINE_ALIGN + CFG.COUNT_ALIGN];
196-
for (int i = 0; i < CFG.SET_COUNT; i++) begin
196+
for (int i = 0; i < CFG.WAY_COUNT; i++) begin
197197
line_hit[i] = ram_rtag[i][CFG.TAG_WIDTH+1] &&
198198
ram_rtag[i][CFG.TAG_WIDTH-1:0] == required_tag;
199199
errors[i] = ram_rtag[i][CFG.TAG_WIDTH] && line_hit[i];
@@ -204,14 +204,14 @@ module snitch_icache_lookup_parallel #(
204204

205205
always_comb begin
206206
for (int i = 0; i < CFG.LINE_WIDTH; i++) begin
207-
automatic logic [CFG.SET_COUNT-1:0] masked;
208-
for (int j = 0; j < CFG.SET_COUNT; j++)
207+
automatic logic [CFG.WAY_COUNT-1:0] masked;
208+
for (int j = 0; j < CFG.WAY_COUNT; j++)
209209
masked[j] = ram_rdata[j][i] & line_hit[j];
210210
data_d.data[i] = |masked;
211211
end
212212
end
213213

214-
lzc #(.WIDTH(CFG.SET_COUNT)) i_lzc (
214+
lzc #(.WIDTH(CFG.WAY_COUNT)) i_lzc (
215215
.in_i ( line_hit ),
216216
.cnt_o ( data_d.cset ),
217217
.empty_o ( )

‎src/snitch_icache_lookup_serial.sv‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ module snitch_icache_lookup_serial #(
4545
input sram_cfg_tag_t sram_cfg_tag_i
4646
);
4747

48-
localparam int unsigned DataAddrWidth = $clog2(CFG.SET_COUNT) + CFG.COUNT_ALIGN;
48+
localparam int unsigned DataAddrWidth = $clog2(CFG.WAY_COUNT) + CFG.COUNT_ALIGN;
4949

5050
`ifndef SYNTHESIS
5151
initial assert(CFG != '0);
@@ -85,8 +85,8 @@ module snitch_icache_lookup_serial #(
8585
logic req_handshake;
8686

8787
logic [CFG.COUNT_ALIGN-1:0] tag_addr;
88-
logic [CFG.SET_COUNT-1:0] tag_enable;
89-
logic [CFG.TAG_WIDTH+1:0] tag_wdata, tag_rdata [CFG.SET_COUNT];
88+
logic [CFG.WAY_COUNT-1:0] tag_enable;
89+
logic [CFG.TAG_WIDTH+1:0] tag_wdata, tag_rdata [CFG.WAY_COUNT];
9090
logic tag_write;
9191

9292
tag_req_t tag_req_d, tag_req_q;
@@ -95,7 +95,7 @@ module snitch_icache_lookup_serial #(
9595
logic tag_handshake;
9696

9797
logic [CFG.TAG_WIDTH-1:0] required_tag;
98-
logic [CFG.SET_COUNT-1:0] line_hit;
98+
logic [CFG.WAY_COUNT-1:0] line_hit;
9999

100100
logic [DataAddrWidth-1:0] lookup_addr;
101101
logic [DataAddrWidth-1:0] write_addr;
@@ -137,7 +137,7 @@ module snitch_icache_lookup_serial #(
137137

138138
// Instantiate the tag sets.
139139
if (CFG.L1_TAG_SCM) begin : gen_scm
140-
for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets
140+
for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : g_sets
141141
register_file_1r_1w #(
142142
.ADDR_WIDTH ($clog2(CFG.LINE_COUNT)),
143143
.DATA_WIDTH (CFG.TAG_WIDTH+2 )
@@ -161,12 +161,12 @@ module snitch_icache_lookup_serial #(
161161
);
162162
end
163163
end else begin : gen_sram
164-
logic [CFG.SET_COUNT*(CFG.TAG_WIDTH+2)-1:0] tag_rdata_flat;
165-
for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : g_sets_rdata
164+
logic [CFG.WAY_COUNT*(CFG.TAG_WIDTH+2)-1:0] tag_rdata_flat;
165+
for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : g_sets_rdata
166166
assign tag_rdata[i] = tag_rdata_flat[i*(CFG.TAG_WIDTH+2)+:CFG.TAG_WIDTH+2];
167167
end
168168
tc_sram_impl #(
169-
.DataWidth ( (CFG.TAG_WIDTH+2) * CFG.SET_COUNT ),
169+
.DataWidth ( (CFG.TAG_WIDTH+2) * CFG.WAY_COUNT ),
170170
.ByteWidth ( CFG.TAG_WIDTH+2 ),
171171
.NumWords ( CFG.LINE_COUNT ),
172172
.NumPorts ( 1 ),
@@ -179,24 +179,24 @@ module snitch_icache_lookup_serial #(
179179
.req_i ( |tag_enable ),
180180
.we_i ( tag_write ),
181181
.addr_i ( tag_addr ),
182-
.wdata_i ( {CFG.SET_COUNT{tag_wdata}} ),
182+
.wdata_i ( {CFG.WAY_COUNT{tag_wdata}} ),
183183
.be_i ( tag_enable ),
184184
.rdata_o ( tag_rdata_flat )
185185
);
186186
end
187187

188188
// Determine which set hit
189-
logic [CFG.SET_COUNT-1:0] errors;
189+
logic [CFG.WAY_COUNT-1:0] errors;
190190
assign required_tag = tag_req_q.addr[CFG.FETCH_AW-1:CFG.LINE_ALIGN + CFG.COUNT_ALIGN];
191-
for (genvar i = 0; i < CFG.SET_COUNT; i++) begin : gen_line_hit
191+
for (genvar i = 0; i < CFG.WAY_COUNT; i++) begin : gen_line_hit
192192
assign line_hit[i] = tag_rdata[i][CFG.TAG_WIDTH+1] &&
193193
tag_rdata[i][CFG.TAG_WIDTH-1:0] == required_tag; // check valid bit and tag
194194
assign errors[i] = tag_rdata[i][CFG.TAG_WIDTH] && line_hit[i]; // check error bit
195195
end
196196
assign tag_rsp_s.hit = |line_hit;
197197
assign tag_rsp_s.error = |errors;
198198

199-
lzc #(.WIDTH(CFG.SET_COUNT)) i_lzc (
199+
lzc #(.WIDTH(CFG.WAY_COUNT)) i_lzc (
200200
.in_i ( line_hit ),
201201
.cnt_o ( tag_rsp_s.cset ),
202202
.empty_o ( )
@@ -282,7 +282,7 @@ module snitch_icache_lookup_serial #(
282282

283283
tc_sram_impl #(
284284
.DataWidth ( CFG.LINE_WIDTH ),
285-
.NumWords ( CFG.LINE_COUNT * CFG.SET_COUNT ),
285+
.NumWords ( CFG.LINE_COUNT * CFG.WAY_COUNT ),
286286
.NumPorts ( 1 ),
287287
.impl_in_t ( sram_cfg_data_t )
288288
) i_data (

‎src/snitch_icache_pkg.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ package snitch_icache_pkg;
1919
int unsigned NR_FETCH_PORTS;
2020
int unsigned LINE_WIDTH;
2121
int unsigned LINE_COUNT;
22-
int unsigned SET_COUNT;
22+
int unsigned WAY_COUNT;
2323
int unsigned PENDING_COUNT;
2424
int unsigned L0_LINE_COUNT;
2525
int unsigned FETCH_AW;

‎src/snitch_read_only_cache.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ module snitch_read_only_cache #(
1414
/// The number of cache lines per set. Power of two; >= 2.
1515
parameter int unsigned LineCount = -1,
1616
/// The set associativity of the cache. Power of two; >= 1.
17-
parameter int unsigned SetCount = 1,
17+
parameter int unsigned WayCount = 1,
1818
/// AXI address width
1919
parameter int unsigned AxiAddrWidth = 0,
2020
/// AXI data width
@@ -194,7 +194,7 @@ module snitch_read_only_cache #(
194194
localparam snitch_icache_pkg::config_t CFG = '{
195195
LINE_WIDTH: LineWidth,
196196
LINE_COUNT: LineCount,
197-
SET_COUNT: SetCount,
197+
WAY_COUNT: WayCount,
198198
PENDING_COUNT: PendingCount,
199199
FETCH_AW: AxiAddrWidth,
200200
FETCH_DW: AxiDataWidth,
@@ -209,7 +209,7 @@ module snitch_read_only_cache #(
209209
FILL_ALIGN: $clog2(AxiDataWidth/8),
210210
LINE_ALIGN: $clog2(LineWidth/8),
211211
COUNT_ALIGN: cf_math_pkg::idx_width(LineCount),
212-
SET_ALIGN: cf_math_pkg::idx_width(SetCount),
212+
SET_ALIGN: cf_math_pkg::idx_width(WayCount),
213213
TAG_WIDTH: AxiAddrWidth - $clog2(LineWidth/8) - $clog2(LineCount) + 1,
214214
ID_WIDTH: 2**AxiIdWidth,
215215
PENDING_IW: $clog2(PendingCount),

‎test/snitch_icache_l0_tb.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ module snitch_icache_l0_tb #(
5757
parameter int L0_LINE_COUNT = 8,
5858
parameter int LINE_WIDTH = 128,
5959
parameter int LINE_COUNT = 0,
60-
parameter int SET_COUNT = 1,
60+
parameter int WAY_COUNT = 1,
6161
parameter int FETCH_AW = AddrWidth,
6262
parameter int FETCH_DW = 32,
6363
parameter int FILL_AW = AddrWidth,
@@ -81,7 +81,7 @@ module snitch_icache_l0_tb #(
8181
LINE_WIDTH: LINE_WIDTH,
8282
LINE_COUNT: LINE_COUNT,
8383
L0_LINE_COUNT: L0_LINE_COUNT,
84-
SET_COUNT: SET_COUNT,
84+
WAY_COUNT: WAY_COUNT,
8585
PENDING_COUNT: 2,
8686
FETCH_AW: FETCH_AW,
8787
FETCH_DW: FETCH_DW,
@@ -96,7 +96,7 @@ module snitch_icache_l0_tb #(
9696
FILL_ALIGN: $clog2(FILL_DW/8),
9797
LINE_ALIGN: $clog2(LINE_WIDTH/8),
9898
COUNT_ALIGN: $clog2(LINE_COUNT),
99-
SET_ALIGN: $clog2(SET_COUNT),
99+
SET_ALIGN: $clog2(WAY_COUNT),
100100
TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8) - $clog2(LINE_COUNT) + 1,
101101
L0_TAG_WIDTH: FETCH_AW - $clog2(LINE_WIDTH/8),
102102
L0_EARLY_TAG_WIDTH:

‎test/snitch_read_only_cache_tb.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ module snitch_read_only_cache_tb #(
249249
parameter int unsigned AxiIdWidth = 5,
250250
parameter int unsigned LineWidth = 256,
251251
parameter int unsigned LineCount = 128,
252-
parameter int unsigned SetCount = 2
252+
parameter int unsigned WayCount = 2
253253
);
254254

255255
localparam time ClkPeriod = 10ns;
@@ -362,7 +362,7 @@ module snitch_read_only_cache_tb #(
362362
snitch_read_only_cache #(
363363
.LineWidth ( LineWidth ),
364364
.LineCount ( LineCount ),
365-
.SetCount ( SetCount ),
365+
.WayCount ( WayCount ),
366366
.AxiAddrWidth ( AxiAddrWidth ),
367367
.AxiDataWidth ( AxiDataWidth ),
368368
.AxiIdWidth ( AxiInIdWidth ),

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