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micprogmicprog
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Add control register file
1 parent 8b0d6a3 commit 797f2dc

7 files changed

Lines changed: 2641 additions & 1 deletion

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‎.github/workflows/lint.yml‎

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@@ -23,6 +23,9 @@ jobs:
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paths: |
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./src
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./test
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exclude_paths: |
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./src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
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./src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
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github_token: ${{ secrets.GITHUB_TOKEN }}
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fail_on_error: true
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reviewdog_reporter: github-check

‎Bender.yml‎

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@@ -16,6 +16,7 @@ dependencies:
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tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 }
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axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }
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scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0 }
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register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
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sources:
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# Source files grouped in levels. Files in level 0 have no dependencies on files in this
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# Level 3
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- src/snitch_icache.sv
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- src/snitch_read_only_cache.sv
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# Level 4
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- files: # ctrl_unit
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- src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv
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- src/ctrl_unit/cluster_icache_ctrl_reg_top.sv
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- src/ctrl_unit/cluster_icache_ctrl_unit.sv
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- target: test
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files:
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- test/snitch_icache_l0_tb.sv

‎Makefile‎

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@@ -9,13 +9,22 @@ VLOG_FLAGS += -svinputport=compat
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VLOG_FLAGS += -suppress 2583
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VLOG_FLAGS += +cover=sbecft
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CTRL_UNIT_DIR = src/ctrl_unit
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CTRL_UNIT = $(CTRL_UNIT_DIR)/cluster_icache_ctrl
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Bender.lock:
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$(BENDER) update
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.bender:
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$(BENDER) checkout
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compile.tcl: .bender
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.PHONY: gen_hw
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gen_hw: .bender $(CTRL_UNIT)_reg_top.sv
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$(CTRL_UNIT)_reg_top.sv: .bender $(CTRL_UNIT).hjson
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python $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py $(CTRL_UNIT).hjson -t $(CTRL_UNIT_DIR) -r
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compile.tcl: .bender Bender.yml Bender.lock
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$(BENDER) script vsim -t test \
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--vlog-arg="$(VLOG_FLAGS)" \
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> compile.tcl

‎src/ctrl_unit/cluster_icache_ctrl.hjson‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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{
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name: "cluster_icache_ctrl",
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clock_primary: "clk_i",
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reset_primary: "rst_ni",
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bus_interfaces: [
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{ protocol: "reg_iface",
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direction: "device"
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}
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],
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param_list: [
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{ name: "NumCores",
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desc: "Number of cores",
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default: "8"
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},
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{ name: "NumAvailableCounters",
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desc: "Number of available counters",
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default: "44" // NumL1Events + NumCores * NumL0Events
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},
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],
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regwidth: "32",
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registers: [
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{ name: "enable",
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desc: "",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "0",
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name: "enable",
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desc: "",
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resval: 0x1
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}
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]
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},
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{ name: "flush",
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desc: "Flush all levels of the cache",
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swaccess: "rw",
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hwaccess: "hrw",
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hwqe: "true",
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hwext: "true",
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fields: [
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{ bits: "0",
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name: "flush",
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desc: "",
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resval: 0x0
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}
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]
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},
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{ name: "flush_l1_only",
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desc: "not yet functional",
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swaccess: "rw",
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hwaccess: "hrw",
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hwext: "true",
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hwqe: "true",
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fields: [
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{ bits: "0",
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name: "flush",
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desc: "",
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resval: 0x0
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}
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]
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},
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{ name: "sel_flush_icache",
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desc: "flush specified L0 banks (and currently the complete L1)",
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swaccess: "rw",
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hwaccess: "hrw",
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hwext: "true",
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hwqe: "true",
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fields: [
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{ bits: "NumCores-1:0",
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name: "flush",
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desc: "",
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resval: 0x0000_0000
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}
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]
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},
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{ name: "clear_counters",
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desc: "Clear all performance counters",
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swaccess: "rw",
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hwaccess: "hrw",
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hwqe: "true",
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hwext: "true",
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fields: [
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{ bits: "0",
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name: "clear",
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desc: "",
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resval: 0x0
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}
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]
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},
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{ name: "enable_counters",
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desc: "Enable performance counters",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "0",
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name: "enable",
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desc: "",
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resval: 0x1
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}
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]
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},
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{ skipto: "0x1C" },
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{ name: "enable_prefetch",
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desc: "Enable prefetching",
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swaccess: "rw",
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hwaccess: "hro",
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fields: [
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{ bits: "0",
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name: "enable",
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desc: "",
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resval: 0x1
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}
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]
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},
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{ multireg: {
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name: "counters",
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desc: "Performance counters",
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count: "NumAvailableCounters",
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cname: "id",
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swaccess: "rw0c",
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hwaccess: "hrw",
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fields: [
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{ bits: "31:0",
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name: "counter",
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desc: "",
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resval: 0x0000_0000
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}
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]
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}
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},
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],
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}

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