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Merge pull request #12 from pulp-platform/michaero/l1_statistics
Add statistics signals for L1
2 parents 91821eb + 813dd9c commit a8ecbff

8 files changed

Lines changed: 131 additions & 88 deletions

‎Changelog.md‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
1313
### Changed
1414
- Rename `SET_COUNT` to `WAY_COUNT` to correct terminology, as it reflects the number of ways in a set.
1515

16+
### Added
17+
- Add statistics signals output for shared L1.
18+
1619
## 0.1.1 - 28.06.2024
1720
### Added
1821
- Allow fetches to bypass prefetches in L1.

‎src/snitch_icache.sv‎

Lines changed: 75 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77

88
`include "common_cells/registers.svh"
99

10-
module snitch_icache #(
10+
module snitch_icache import snitch_icache_pkg::*; #(
1111
/// Number of request (fetch) ports
1212
parameter int unsigned NR_FETCH_PORTS = -1,
1313
/// L0 Cache Line Count (L0 is fully associative)
@@ -61,8 +61,9 @@ module snitch_icache #(
6161
input logic clk_d2_i,
6262
input logic rst_ni,
6363

64-
input logic enable_prefetching_i,
65-
output snitch_icache_pkg::icache_events_t [NR_FETCH_PORTS-1:0] icache_events_o,
64+
input logic enable_prefetching_i,
65+
output icache_l0_events_t [NR_FETCH_PORTS-1:0] icache_l0_events_o,
66+
output icache_l1_events_t icache_l1_events_o,
6667

6768
input logic [NR_FETCH_PORTS-1:0] flush_valid_i,
6869
output logic [NR_FETCH_PORTS-1:0] flush_ready_o,
@@ -235,25 +236,25 @@ module snitch_icache #(
235236
) i_snitch_icache_l0 (
236237
.clk_i ( clk_d2_i ),
237238
.rst_ni,
238-
.flush_valid_i ( flush_valid_i[i] ),
239+
.flush_valid_i ( flush_valid_i [i] ),
239240
.enable_prefetching_i,
240-
.icache_events_o ( icache_events_o [i] ),
241-
.in_addr_i ( inst_addr_i [i] ),
242-
.in_data_o ( in_cache_data [i] ),
243-
.in_error_o ( in_cache_error [i] ),
244-
.in_valid_i ( in_cache_valid [i] ),
245-
.in_ready_o ( in_cache_ready [i] ),
246-
247-
.out_req_addr_o ( local_prefetch_req.addr ),
248-
.out_req_id_o ( local_prefetch_req.id ),
241+
.icache_events_o ( icache_l0_events_o [i] ),
242+
.in_addr_i ( inst_addr_i [i] ),
243+
.in_data_o ( in_cache_data [i] ),
244+
.in_error_o ( in_cache_error [i] ),
245+
.in_valid_i ( in_cache_valid [i] ),
246+
.in_ready_o ( in_cache_ready [i] ),
247+
248+
.out_req_addr_o ( local_prefetch_req.addr ),
249+
.out_req_id_o ( local_prefetch_req.id ),
249250
.out_req_valid_o ( local_prefetch_req_valid ),
250251
.out_req_ready_i ( local_prefetch_req_ready ),
251252

252-
.out_rsp_data_i ( local_prefetch_rsp.data ),
253-
.out_rsp_error_i ( local_prefetch_rsp.error ),
254-
.out_rsp_id_i ( local_prefetch_rsp.id ),
255-
.out_rsp_valid_i ( local_prefetch_rsp_valid ),
256-
.out_rsp_ready_o ( local_prefetch_rsp_ready )
253+
.out_rsp_data_i ( local_prefetch_rsp.data ),
254+
.out_rsp_error_i ( local_prefetch_rsp.error ),
255+
.out_rsp_id_i ( local_prefetch_rsp.id ),
256+
.out_rsp_valid_i ( local_prefetch_rsp_valid ),
257+
.out_rsp_ready_o ( local_prefetch_rsp_ready )
257258
);
258259

259260
isochronous_spill_register #(
@@ -527,75 +528,77 @@ module snitch_icache #(
527528

528529
if (SERIAL_LOOKUP) begin : gen_serial_lookup
529530
snitch_icache_lookup_serial #(
530-
.CFG (CFG),
531-
.sram_cfg_tag_t (sram_cfg_tag_t),
532-
.sram_cfg_data_t (sram_cfg_data_t)
531+
.CFG ( CFG ),
532+
.sram_cfg_tag_t ( sram_cfg_tag_t ),
533+
.sram_cfg_data_t ( sram_cfg_data_t )
533534
) i_lookup (
534535
.clk_i,
535536
.rst_ni,
536537

537-
.flush_valid_i (flush_valid_lookup ),
538-
.flush_ready_o (flush_ready_lookup ),
539-
540-
.in_addr_i ( prefetch_lookup_req.addr ),
541-
.in_id_i ( prefetch_lookup_req.id ),
542-
.in_valid_i ( prefetch_lookup_req_valid ),
543-
.in_ready_o ( prefetch_lookup_req_ready ),
544-
545-
.out_addr_o ( lookup_addr ),
546-
.out_id_o ( lookup_id ),
547-
.out_set_o ( lookup_set ),
548-
.out_hit_o ( lookup_hit ),
549-
.out_data_o ( lookup_data ),
550-
.out_error_o ( lookup_error ),
551-
.out_valid_o ( lookup_valid ),
552-
.out_ready_i ( lookup_ready ),
553-
554-
.write_addr_i ( write_addr ),
555-
.write_set_i ( write_set ),
556-
.write_data_i ( write_data ),
557-
.write_tag_i ( write_tag ),
558-
.write_error_i ( write_error ),
559-
.write_valid_i ( write_valid ),
560-
.write_ready_o ( write_ready ),
538+
.flush_valid_i ( flush_valid_lookup ),
539+
.flush_ready_o ( flush_ready_lookup ),
540+
.icache_events_o ( icache_l1_events_o ),
541+
542+
.in_addr_i ( prefetch_lookup_req.addr ),
543+
.in_id_i ( prefetch_lookup_req.id ),
544+
.in_valid_i ( prefetch_lookup_req_valid ),
545+
.in_ready_o ( prefetch_lookup_req_ready ),
546+
547+
.out_addr_o ( lookup_addr ),
548+
.out_id_o ( lookup_id ),
549+
.out_set_o ( lookup_set ),
550+
.out_hit_o ( lookup_hit ),
551+
.out_data_o ( lookup_data ),
552+
.out_error_o ( lookup_error ),
553+
.out_valid_o ( lookup_valid ),
554+
.out_ready_i ( lookup_ready ),
555+
556+
.write_addr_i ( write_addr ),
557+
.write_set_i ( write_set ),
558+
.write_data_i ( write_data ),
559+
.write_tag_i ( write_tag ),
560+
.write_error_i ( write_error ),
561+
.write_valid_i ( write_valid ),
562+
.write_ready_o ( write_ready ),
561563

562564
.sram_cfg_tag_i,
563565
.sram_cfg_data_i
564566
);
565567

566568
end else begin : gen_parallel_lookup
567569
snitch_icache_lookup_parallel #(
568-
.CFG (CFG),
569-
.sram_cfg_tag_t (sram_cfg_tag_t),
570-
.sram_cfg_data_t (sram_cfg_data_t)
570+
.CFG ( CFG ),
571+
.sram_cfg_tag_t ( sram_cfg_tag_t ),
572+
.sram_cfg_data_t ( sram_cfg_data_t )
571573
) i_lookup (
572574
.clk_i,
573575
.rst_ni,
574576

575-
.flush_valid_i (flush_valid_lookup ),
576-
.flush_ready_o (flush_ready_lookup ),
577-
578-
.in_addr_i ( prefetch_lookup_req.addr ),
579-
.in_id_i ( prefetch_lookup_req.id ),
580-
.in_valid_i ( prefetch_lookup_req_valid ),
581-
.in_ready_o ( prefetch_lookup_req_ready ),
582-
583-
.out_addr_o ( lookup_addr ),
584-
.out_id_o ( lookup_id ),
585-
.out_set_o ( lookup_set ),
586-
.out_hit_o ( lookup_hit ),
587-
.out_data_o ( lookup_data ),
588-
.out_error_o ( lookup_error ),
589-
.out_valid_o ( lookup_valid ),
590-
.out_ready_i ( lookup_ready ),
591-
592-
.write_addr_i ( write_addr ),
593-
.write_set_i ( write_set ),
594-
.write_data_i ( write_data ),
595-
.write_tag_i ( write_tag ),
596-
.write_error_i ( write_error ),
597-
.write_valid_i ( write_valid ),
598-
.write_ready_o ( write_ready ),
577+
.flush_valid_i ( flush_valid_lookup ),
578+
.flush_ready_o ( flush_ready_lookup ),
579+
.icache_events_o ( icache_l1_events_o ),
580+
581+
.in_addr_i ( prefetch_lookup_req.addr ),
582+
.in_id_i ( prefetch_lookup_req.id ),
583+
.in_valid_i ( prefetch_lookup_req_valid ),
584+
.in_ready_o ( prefetch_lookup_req_ready ),
585+
586+
.out_addr_o ( lookup_addr ),
587+
.out_id_o ( lookup_id ),
588+
.out_set_o ( lookup_set ),
589+
.out_hit_o ( lookup_hit ),
590+
.out_data_o ( lookup_data ),
591+
.out_error_o ( lookup_error ),
592+
.out_valid_o ( lookup_valid ),
593+
.out_ready_i ( lookup_ready ),
594+
595+
.write_addr_i ( write_addr ),
596+
.write_set_i ( write_set ),
597+
.write_data_i ( write_data ),
598+
.write_tag_i ( write_tag ),
599+
.write_error_i ( write_error ),
600+
.write_valid_i ( write_valid ),
601+
.write_ready_o ( write_ready ),
599602

600603
.sram_cfg_tag_i,
601604
.sram_cfg_data_i

‎src/snitch_icache_l0.sv‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -17,14 +17,14 @@ module snitch_icache_l0 import snitch_icache_pkg::*; #(
1717
input logic rst_ni,
1818
input logic flush_valid_i,
1919

20-
input logic enable_prefetching_i,
21-
output icache_events_t icache_events_o,
22-
23-
input logic [CFG.FETCH_AW-1:0] in_addr_i,
24-
input logic in_valid_i,
25-
output logic [CFG.FETCH_DW-1:0] in_data_o,
26-
output logic in_ready_o,
27-
output logic in_error_o,
20+
input logic enable_prefetching_i,
21+
output icache_l0_events_t icache_events_o,
22+
23+
input logic [CFG.FETCH_AW-1:0] in_addr_i,
24+
input logic in_valid_i,
25+
output logic [CFG.FETCH_DW-1:0] in_data_o,
26+
output logic in_ready_o,
27+
output logic in_error_o,
2828

2929
output logic [CFG.FETCH_AW-1:0] out_req_addr_o,
3030
output logic [CFG.ID_WIDTH-1:0] out_req_id_o,

‎src/snitch_icache_lookup_parallel.sv‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
66

77
/// An actual cache lookup.
8-
module snitch_icache_lookup_parallel #(
9-
parameter snitch_icache_pkg::config_t CFG = '0,
8+
module snitch_icache_lookup_parallel import snitch_icache_pkg::*; #(
9+
parameter config_t CFG = '0,
1010
/// Configuration input types for SRAMs used in implementation.
1111
parameter type sram_cfg_data_t = logic,
1212
parameter type sram_cfg_tag_t = logic
@@ -16,6 +16,7 @@ module snitch_icache_lookup_parallel #(
1616

1717
input logic flush_valid_i,
1818
output logic flush_ready_o,
19+
output icache_l1_events_t icache_events_o,
1920

2021
input logic [CFG.FETCH_AW-1:0] in_addr_i,
2122
input logic [CFG.ID_WIDTH-1:0] in_id_i,
@@ -250,6 +251,17 @@ module snitch_icache_lookup_parallel #(
250251
assign out_error_o = data_q.error;
251252
assign out_valid_o = buffer_valid;
252253

254+
// ------------------
255+
// Performance Events
256+
// ------------------
257+
always_comb begin
258+
icache_events_o = '0;
259+
icache_events_o.l1_miss = valid_q & ~data_d.hit;
260+
icache_events_o.l1_hit = valid_q & data_d.hit;
261+
icache_events_o.l1_stall = in_valid_i & ~in_ready_o;
262+
icache_events_o.l1_handler_stall = out_valid_o & ~out_ready_i;
263+
end
264+
253265
// Assertions
254266
`include "common_cells/assertions.svh"
255267
`ASSERT(i_rsp_buffer_ready, (valid_q |-> buffer_ready), clk_i, !rst_ni)

‎src/snitch_icache_lookup_serial.sv‎

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
`include "common_cells/registers.svh"
88

99
/// An actual cache lookup.
10-
module snitch_icache_lookup_serial #(
11-
parameter snitch_icache_pkg::config_t CFG = '0,
10+
module snitch_icache_lookup_serial import snitch_icache_pkg::*; #(
11+
parameter config_t CFG = '0,
1212
/// Configuration input types for SRAMs used in implementation.
1313
parameter type sram_cfg_data_t = logic,
1414
parameter type sram_cfg_tag_t = logic
@@ -18,6 +18,7 @@ module snitch_icache_lookup_serial #(
1818

1919
input logic flush_valid_i,
2020
output logic flush_ready_o,
21+
output icache_l1_events_t icache_events_o,
2122

2223
input logic [CFG.FETCH_AW-1:0] in_addr_i,
2324
input logic [CFG.ID_WIDTH-1:0] in_id_i,
@@ -334,4 +335,15 @@ module snitch_icache_lookup_serial #(
334335
assign out_valid_o = data_valid;
335336
assign data_ready = out_ready_i;
336337

338+
// ------------------
339+
// Performance Events
340+
// ------------------
341+
always_comb begin
342+
icache_events_o = '0;
343+
icache_events_o.l1_miss = req_handshake & ~tag_rsp_s.hit;
344+
icache_events_o.l1_hit = req_handshake & tag_rsp_s.hit;
345+
icache_events_o.l1_stall = in_valid_i & ~in_ready_o;
346+
icache_events_o.l1_handler_stall = out_valid_o & ~out_ready_i;
347+
end
348+
337349
endmodule

‎src/snitch_icache_pkg.sv‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,14 @@ package snitch_icache_pkg;
1212
logic l0_prefetch;
1313
logic l0_double_hit;
1414
logic l0_stall;
15-
} icache_events_t;
15+
} icache_l0_events_t;
16+
17+
typedef struct packed {
18+
logic l1_miss;
19+
logic l1_hit;
20+
logic l1_stall;
21+
logic l1_handler_stall;
22+
} icache_l1_events_t;
1623

1724
typedef struct packed {
1825
// Parameters passed to the root module.

‎src/snitch_read_only_cache.sv‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
/// Serve read memory requests from a read-only cache.
99
/// The cacheable region can be runtime configured. All writes and read
1010
/// requests outside the configured regions will be forwarded.
11-
module snitch_read_only_cache #(
11+
module snitch_read_only_cache import snitch_icache_pkg::*; #(
1212
/// Cache Line Width
1313
parameter int unsigned LineWidth = -1,
1414
/// The number of cache lines per set. Power of two; >= 2.
@@ -39,6 +39,7 @@ module snitch_read_only_cache #(
3939
input logic enable_i,
4040
input logic flush_valid_i,
4141
output logic flush_ready_o,
42+
output icache_l1_events_t icache_events_o,
4243
input logic [NrAddrRules-1:0][AxiAddrWidth-1:0] start_addr_i,
4344
input logic [NrAddrRules-1:0][AxiAddrWidth-1:0] end_addr_i,
4445
input slv_req_t axi_slv_req_i,
@@ -191,7 +192,7 @@ module snitch_read_only_cache #(
191192
// Cache Logic
192193
// --------------------------------------------------
193194
localparam int unsigned PendingCount = MaxTrans;
194-
localparam snitch_icache_pkg::config_t CFG = '{
195+
localparam config_t CFG = '{
195196
LINE_WIDTH: LineWidth,
196197
LINE_COUNT: LineCount,
197198
WAY_COUNT: WayCount,
@@ -293,6 +294,7 @@ module snitch_read_only_cache #(
293294

294295
.flush_valid_i ( flush_valid_i ),
295296
.flush_ready_o ( flush_ready_o ),
297+
.icache_events_o,
296298

297299
.in_addr_i ( in_addr ),
298300
.in_id_i ( in_id ),
@@ -330,6 +332,7 @@ module snitch_read_only_cache #(
330332

331333
.flush_valid_i ( flush_valid_i ),
332334
.flush_ready_o ( flush_ready_o ),
335+
.icache_events_o,
333336

334337
.in_addr_i ( in_addr ),
335338
.in_id_i ( in_id ),

‎test/snitch_read_only_cache_tb.sv‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -379,12 +379,15 @@ module snitch_read_only_cache_tb #(
379379
.enable_i ( 1'b1 ),
380380
.flush_valid_i ( 1'b0 ),
381381
.flush_ready_o ( /*unused*/ ),
382+
.icache_events_o ( ),
382383
.start_addr_i ( {CachedRegionStart} ),
383384
.end_addr_i ( {CachedRegionEnd} ),
384385
.axi_slv_req_i ( axi_mst_req ),
385386
.axi_slv_rsp_o ( axi_mst_resp ),
386387
.axi_mst_req_o ( axi_slv_req ),
387-
.axi_mst_rsp_i ( axi_slv_resp )
388+
.axi_mst_rsp_i ( axi_slv_resp ),
389+
.sram_cfg_data_i('0),
390+
.sram_cfg_tag_i ('0)
388391
);
389392

390393
task static cycle_start;

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