Add L1 error count registers

Author: micprog

src/ctrl_unit/cluster_icache_ctrl.hjson

@@ -17,6 +17,14 @@
       desc: "Number of cores",
       default: "8"
     },
+    { name: "NumL0Events",
+      desc: "Number of L0 events",
+      default: "5"
+    },
+    { name: "NumL1Events",
+      desc: "Number of L1 events",
+      default: "4"
+    },
     { name: "NumAvailableCounters",
       desc: "Number of available counters",
       default: "44" // NumL1Events + NumCores * NumL0Events

src/ctrl_unit/cluster_icache_ctrl_reg_pkg.sv

@@ -8,6 +8,8 @@ package cluster_icache_ctrl_reg_pkg;
 
   // Param list
   parameter int NumCores = 8;
+  parameter int NumL0Events = 5;
+  parameter int NumL1Events = 4;
   parameter int NumAvailableCounters = 44;
 
   // Address widths within the block

src/ctrl_unit/cluster_icache_ctrl_unit.sv

@@ -26,9 +26,9 @@ module cluster_icache_ctrl_unit import snitch_icache_pkg::*; #(
   import cluster_icache_ctrl_reg_pkg::*;
 
   initial begin
-    assert(5 == $bits(icache_l0_events_t));
-    assert(4 == $bits(icache_l1_events_t));
-    assert(NumAvailableCounters >= 4 + NR_FETCH_PORTS*5);
+    assert(NumL0Events == $bits(icache_l0_events_t));
+    assert(NumL1Events == $bits(icache_l1_events_t));
+    assert(NumAvailableCounters >= NumL1Events + NR_FETCH_PORTS*NumL0Events);
     assert(NR_FETCH_PORTS <= NumCores);
   end
 
@@ -66,11 +66,16 @@ module cluster_icache_ctrl_unit import snitch_icache_pkg::*; #(
     counters_reg[3].de = reg2hw.enable_counters.q & l1_events_i.l1_handler_stall;
 
     for (int unsigned i = 0; i < NR_FETCH_PORTS; i++) begin
-      counters_reg[4 + i*5 + 0].de = reg2hw.enable_counters.q & l0_events_i[i].l0_miss;
-      counters_reg[4 + i*5 + 1].de = reg2hw.enable_counters.q & l0_events_i[i].l0_hit;
-      counters_reg[4 + i*5 + 2].de = reg2hw.enable_counters.q & l0_events_i[i].l0_prefetch;
-      counters_reg[4 + i*5 + 3].de = reg2hw.enable_counters.q & l0_events_i[i].l0_double_hit;
-      counters_reg[4 + i*5 + 4].de = reg2hw.enable_counters.q & l0_events_i[i].l0_stall;
+      counters_reg[NumL1Events + i*NumL0Events + 0].de = reg2hw.enable_counters.q &
+                                                         l0_events_i[i].l0_miss;
+      counters_reg[NumL1Events + i*NumL0Events + 1].de = reg2hw.enable_counters.q &
+                                                         l0_events_i[i].l0_hit;
+      counters_reg[NumL1Events + i*NumL0Events + 2].de = reg2hw.enable_counters.q &
+                                                         l0_events_i[i].l0_prefetch;
+      counters_reg[NumL1Events + i*NumL0Events + 3].de = reg2hw.enable_counters.q &
+                                                         l0_events_i[i].l0_double_hit;
+      counters_reg[NumL1Events + i*NumL0Events + 4].de = reg2hw.enable_counters.q &
+                                                         l0_events_i[i].l0_stall;
     end
 
     // Clear on global clear signal